FM24C256-GTR Ramtron, FM24C256-GTR Datasheet - Page 7

• Manufacturer Part Number: FM24C256-GTR
• Description: fm24c256 series 256 k-bit (32k x 8) 5 v 3 us serial...
• Manufacturer: Ramtron

Endurance
A FRAM internally operates with a read and restore
mechanism. Therefore, endurance cycles are applied
for each read and write access. The FRAM
architecture is based on an array of rows and
columns. Rows (A14-A6) are subdivided into 8
segments (A5-A3). Each access causes an endurance
cycle for a row segment. In the FM24C256, there are
Rev 3.1
May 2005
By FM24C256
By FM24C256
By Master
By Master
Start
S
Slave Address
Start
S
By FM24C256
By Master
Slave Address
0
A
Address
Address MSB
Start
Address
S
Acknowledge
Figure 9. Selective (Random) Read
Figure 7. Current Address Read
1
Slave Address
Figure 8. Sequential Read
A
Address
A
Address LSB
Acknowledge
Acknowledge
Data Byte
1
A
8 bytes per segment. Endurance can be optimized by
ensuring frequently accessed data is located in
different segments. Regardless, FRAM read and
write endurance is effectively unlimited at the 1MHz
two-wire speed. Even at 30 accesses per second to
the same segment, 10 years time will elapse before
10 billion endurance cycles occur.
Data Byte
Acknowledge
A
Data
Start
S
A
Data
Acknowledge
Slave Address
Address
No
1
Data Byte
P
1
A
Stop
Acknowledge
Data Byte
No
1 P
Data
Acknowledge
FM24C256
No
1 P
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