FM24C04A-GTR Ramtron, FM24C04A-GTR Datasheet
FM24C04A-GTR
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FM24C04A-GTR Summary of contents
Page 1
... The FM24C04A provides substantial benefits to users of serial EEPROM, yet these benefits are available in a hardware drop-in replacement. The FM24C04A is available in industry standard 8-pin packages using a two-wire protocol. The specifications are guaranteed over an industrial temperature range of -40°C to +85° ...
Page 2
... Write Protect: When WP is high the entire array is write-protected. When WP is low, all addresses may be written. This pin is internally pulled down connect VDD Supply Supply Voltage: 5V VSS Supply Ground Rev. 3.0 Mar. 2005 Address Latch Figure 1. Block Diagram FM24C04A 128 x 32 FRAM Array 8 Data Latch ...
Page 3
... This is explained in more detail in the interface section below. Users can expect several obvious system benefits from the FM24C04A due to its fast write cycle and high endurance as compared with EEPROM. However there are less obvious benefits as well. For example in a high noise environment, the fast-write operation is less susceptible to corruption than an EEPROM since it is completed quickly ...
Page 4
... When a read operation is complete and no more data is needed, the receiver must not acknowledge acknowledges the last byte, this will cause the FM24C04A to attempt to drive the bus on the next clock while the master is sending a new command such as a Stop command. Slave Address The first byte that the FM24C04A expects after a start condition is the slave address ...
Page 5
... After all address information has been transmitted, data transfer between the bus master and the FM24C04A can begin. For a read operation the FM24C04A will place 8 data bits on the bus then wait for an acknowledge. If the acknowledge occurs, the next sequential byte will be transferred. If the acknowledge is not sent, the read operation is concluded ...
Page 6
... Current Address & Sequential Read The FM24C04A uses an internal latch to supply the lower 8 address bits for a read operation. A current address read uses the existing value in the address latch as a starting place for the read operation ...
Page 7
... By FM24C04A Address Start By Master S Slave Address FM24C04A Endurance Internally, a FRAM operates with a read and restore mechanism. Therefore, endurance cycles are applied for each read or write cycle. The FRAM architecture is based on an array of rows and columns. Rows are Rev. 3.0 Mar. 2005 ...
Page 8
... DD Min Typ 4.5 5.0 115 400 800 1 -0 other inputs -0. Stop command issued FM24C04A Ratings -1.0V to +7.0V -1.0V to +7.0V and V < V +1. - 125 C 300 C 3kV 300V MSL-1 Max Units Notes 5 150 A 500 A 1000 A 10 ...
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... Min 0 100 0 4.7 1.3 4.0 0.6 3 4.7 1.3 4.0 0.6 4.7 0 250 100 1000 300 4.0 0 5V) DD Max Units FM24C04A Max Min Max Units Notes 400 0 1000 kHz 0.6 s 0.4 s 0.9 0.55 s 0.5 s 0. 100 ns 300 300 ns 1 300 100 ...
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... SU:STO SDA Start Data Retention (V = 4.5V to 5.5V, + Parameter Data Retention Rev. 3.0 Mar. 2005 t HIGH 1/fSCL t AA Stop Start t HD:DAT t t SU:DAT HD:STA Stop Start Min Units 45 Years FM24C04A LOW t HD:DAT t SU:DAT t DH Acknowledge t AA Acknowledge Notes ...
Page 11
... SOIC Package Marking Scheme Legend: XXXX= part number, P= package type LLLLLLL= lot code XXXXXXX-P LLLLLLL RIC=Ramtron Int’l Corp, YY=year, WW=work week RICYYWW Example: FM24C04A, Standard SOIC package, Year 2004, Work Week 39 FM24C04A-S A40003S RIC0439 Rev. 3.0 Mar. 2005 Recommended PCB Footprint 3.90 ...
Page 12
... Changed to Production status. Added “green” packaging option. Changed input leakage spec to 1uA. Changed Data Retention spec. Added ESD and package MSL ratings. Modified note 3 (input leakage table. Updated package drawing. Updated rev numbering and footer. Removed applications section. FM24C04A ...