MX29LV400CBTC-70G Macronix, MX29LV400CBTC-70G Datasheet - Page 21

• Manufacturer Part Number: MX29LV400CBTC-70G
• Description: MX29LV Series 3 V 4 Mb (524k x 8/256k x 16) 70 ns Parallel Flash - TSOP-48
• Manufacturer: Macronix

AUTOMATIC SELECT OPERATION
When the device is in Read array mode, erase-suspended read array mode or CFI mode, user can issue read
silicon ID command to enter read silicon ID mode. After entering read silicon ID mode, user can query several
silicon IDs continuously and does not need to issue read silicon ID mode again. When A0 is Low, device will out-
put Macronix Manufacture ID C2. When A0 is high, device will output Device ID. In read silicon ID mode, issuing
reset command will reset device back to read array mode or erase-suspended read array mode.
Another way to enter read silicon ID is to apply high voltage on A9 pin with CE#, OE#, A6 and A1 at Vil. While
the high voltage of A9 pin is discharged, device will automatically leave read silicon ID mode and go back to read
array mode or erase-suspended read array mode. When A0 is Low, device will output Macronix Manufacture ID
C2. When A0 is high, device will output Device ID.
VERIFY SECTOR PROTECT STATUS OPERATION
MX29LV400C/MX29LV800C/MX29LV160C T/B provides hardware sector protection against Program and Erase
operation for protected sectors. The sector protect status can be read through Sector Protect Verify command.
This method requires Vhv on A9 pin, Vih on WE# and A1 pins, Vil on CE#, OE#, A6 and A0 pins, and sector ad-
dress on A12 to Am pins. If the read out data is 01H, the designated sector is protected. Oppositely, if the read
out data is 00H, the designated sector is not protected.
DATA PROTECTION
To avoid accidental erasure or programming of the device, the device is automatically reset to read array mode
during power up. Besides, only after successful completion of the specified command sets will the device begin
its erase or program operation.
Other features to protect the data from accidental alternation are described as followed.
LOW VCC WRITE INHIBIT
The device refuses to accept any write command when Vcc is less than 1.4V. This prevents data from spuriously
altered. The device automatically resets itself when Vcc is lower than 1.4V and write cycles are ignored until Vcc
is greater than 1.4V. System must provide proper signals on control pins after Vcc is larger than 1.4V to avoid
unintentional program or erase operation
WRITE PULSE "GLITCH" PROTECTION
CE#, WE#, OE# pulses shorter than 5ns are treated as glitches and will not be regarded as an effective write
cycle.
LOGICAL INHIBIT
A valid write cycle requires both CE# and WE# at Vil with OE# at Vih. Write cycle is ignored when either CE# at
Vih, WE# a Vih, or OE# at Vil.
P/N:PM1300
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MX29LV400C T/B
MX29LV800C T/B
MX29LV160C T/B
REV. 2.6, DEC. 22, 2011