SY58027UMI Micrel Inc, SY58027UMI Datasheet - Page 5

• Manufacturer Part Number: SY58027UMI
• Description: IC MUX DUAL 2:1 DFF LVPECL 32MLF
• Manufacturer: Micrel Inc
• Series: SY58r
• Type: Multiplexerr

Specifications of SY58027UMI

• Circuit: 1 x 2:1
• Independent Circuits: 2
• Voltage Supply Source: Single Supply
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-MLF®, QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output High, Low: -

Micrel, Inc.
V
Symbol
f
t
t
t
t
Notes:
7. High-speed AC parameters are guaranteed by design and characterization. V
8. Input-to-input skew is the difference in time between two inputs to the output within a bank.
9. Bank-to-bank skew is the difference in time from input to the output between bank.
10. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the
11. Random jitter is measured with a K28.7 comma detect character pattern, measured at 5Gbps and 2.5Gbps/3.2Gbps.
12. Deterministic jitter is measured at 2.5Gbps/3.2Gbps, with both K28.5 and 2
13. Cycle-to-cycle jitter definition: the variation of periods between adjacent cycles, T
14. Total jitter definition: with an ideal clock input of frequency - f
15. Crosstalk is measured at the output while applying two similar frequencies that are asynchronous with respect to each other at the inputs.
M9999-082707
[e-mail] or [phone]
MAX
pd
SKEW
JITTER
r
, t
CC
AC ELECTRICAL CHARACTERISTICS
f
respective inputs.
signal.
specified peak-to-peak jitter value.
TRUTH TABLES
= 2.5V ±5% or 3.3V ±10%; T
INA0
INB0
X
X
X
X
0
1
0
1
Parameter
Maximum Operating Frequency
Propagation Delay
Input-to-Input Skew (Within-bank)
Bank-to-Bank Skew
Part-to-Part Skew
Data
Clock
Crosstalk-Induced Jitter
Output Rise/Fall Time 20% to 80%
Cycle-to-Cycle Jitter (RJ)
/INA0
/INB0
Deterministic Jitter (DJ)
1
0
X
X
1
0
X
X
Channel-to-Channel
Random Jitter (RJ)
A
= –40°C to +85°C; R
Total Jitter (TJ)
SEL-to-Q
IN-to-Q
INA1
INB1
X
X
X
X
0
1
0
1
Condition
V
V
Note 8
Note 9
Note 10
Note 11
Note 12
Note 13
Note 14
Note 15, Within-bank.
At full swing.
L
OUT
IN
(7)
MAX
= 50ý to V
ž 300mV
ž 200mV
, no more than one output edge in 10
/INA1
/INB1
5
CC
X
X
X
X
1
0
1
0
23
–2V, unless otherwise stated.
–1 PRBS pattern.
IN
swing ž 100mV unless otherwise noted.
n
–T
n–1
where T is the time between rising edges of the output
SELA
SELB
0
0
1
1
0
0
1
1
NRZ Data
Clock
12
output edges will deviate by more than the
10.7
Min
140
100
20
QA
QB
0
1
0
1
0
1
0
1
Typ
215
220
55
7
6
8
Precision Edge
Max
290
400
100
0.7
15
20
10
10
80
1
1
/QA
/QB
SY58027U
1
0
1
0
1
0
1
0
ps
ps
ps
Units
Gbps
ps
ps
GHz
ps
ps
ps
ps
ps
ps
RMS
RMS
RMS
PP
PP
®