NH82801GBM S L8YB Intel, NH82801GBM S L8YB Datasheet
NH82801GBM S L8YB
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NH82801GBM S L8YB Summary of contents
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... Intel I/O Controller Hub 7 (ICH7) Family Datasheet ® — For the Intel 82801GB ICH7, 82801GR ICH7R, 82801GDH ICH7DH, 82801GBM ICH7-M, 82801GHM ICH7-M DH, and 82801GU ICH7-U I/O Controller Hubs April 2007 Document Number: 307013-003 ...
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... Corporation. Alert on LAN is a result of the Intel-IBM Advanced Manageability Alliance and a trademark of IBM. Intel, Intel SpeedStep, and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. ...
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... Other Clocks..................................................................................................... 69 2.18 Miscellaneous Signals ........................................................................................ 70 ® 2.19 AC ’97/Intel High Definition Audio Link ............................................................... 71 2.20 Serial Peripheral Interface (SPI) (Desktop and Mobile Only) .................................... 72 ® 2.21 Intel Quick Resume Technology (Intel 2.22 General Purpose I/O Signals ............................................................................... 72 2.23 Power and Ground ............................................................................................. 74 2.24 Pin Straps ........................................................................................................ 76 2.24.1 Functional Straps ................................................................................... 76 2.24.2 External RTC Circuitry ............................................................................. 78 ® 3 Intel ICH7 Pin States............................................................................................. 79 3 ...
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... SIZE...................................................................................... 120 5.5.1.5 SYNC..................................................................................... 121 5.5.1.6 SYNC Time-Out ....................................................................... 121 5.5.1.7 SYNC Error Indication .............................................................. 121 5.5.1.8 LFRAME# Usage...................................................................... 122 5.5.1.9 I/O Cycles .............................................................................. 122 5.5.1.10 Bus Master Cycles ................................................................... 122 5.5.1.11 LPC Power Management ........................................................... 122 5.5.1.12 Configuration and Intel 5.5.2 SERR# Generation ................................................................................ 123 4 ® 82562EM/EX ................................................................. 117 ® ICH7 Implications................................. 123 ® Intel ICH7 Family Datasheet ...
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... Special Mask Mode.................................................................. 139 5.9.6 Steering PCI Interrupts ......................................................................... 139 5.10 Advanced Programmable Interrupt Controller (APIC) (D31:F0) .............................. 140 5.10.1 Interrupt Handling................................................................................ 140 5.10.2 Interrupt Mapping ................................................................................ 140 5.10.3 PCI / PCI Express* Message-Based Interrupts .......................................... 141 5.10.4 Front Side Bus Interrupt Delivery ........................................................... 141 5.10.4.1 Edge-Triggered Operation......................................................... 142 ® Intel ICH7 Family Datasheet 5 ...
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... Power Management ................................................................. 152 5.14 Power Management (D31:F0) ............................................................................ 153 5.14.1 Features .............................................................................................. 153 ® 5.14.2 Intel ICH7 and System Power States ..................................................... 153 5.14.3 System Power Planes ............................................................................ 156 5.14.4 SMI#/SCI Generation ............................................................................ 156 5.14.4.1 PCI Express* SCI (Desktop and Mobile Only) .............................. 159 5.14.4.2 PCI Express* Hot-Plug (Desktop and Mobile Only) ....................... 159 5 ...
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... Low) (Mobile/Ultra Mobile Only)..................... 175 5.14.11.7Controlling Leakage and Power Consumption during Low-Power States ................................................................................... 175 5.14.12Clock Generators.................................................................................. 176 5.14.12.1Clock Control Signals from Intel Synthesizer (Mobile/Ultra Mobile Only)....................................... 176 5.14.13Legacy Power Management Theory of Operation ....................................... 177 5.14.13.1APM Power Management (Desktop Only) .................................... 177 5 ...
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... Power Management Operation ................................................................ 194 5.17.4.1 Power State Mappings.............................................................. 194 5.17.4.2 Power State Transitions ............................................................ 195 5.17.4.3 SMI Trapping (APM) ................................................................. 196 5.17.5 SATA LED ............................................................................................ 196 5.17.6 AHCI Operation (Intel 5.17.7 Serial ATA Reference Clock Low Power Request (SATACLKREQ#) ................. 197 5.18 High Precision Event Timers .............................................................................. 197 5.18.1 Timer Accuracy..................................................................................... 197 5.18.2 Interrupt Mapping................................................................................. 198 5 ...
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... ICH7 Family Datasheet ® ICH7 as SMBus Master)............................. 224 ® AMT) (Desktop and Mobile Only)....... 244 ® ICH7 and Intel PRO 82573E ....................... 245 ® ICH7 SPI Based BIOS Only Configuration Requirements ® ® ICH7 with Intel PRO 82573E with Intel AMT Firmware ...
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... RP4D—Root Port 4 Descriptor Register..................................................... 273 7.1.23 RP4BA—Root Port 4 Base Address Register ............................................... 273 ® 7.1.24 HDD—Intel 7.1.25 HDBA—Intel 7.1.26 RP5D—Root Port 5 Descriptor Register..................................................... 274 7.1.27 RP5BA—Root Port 5 Base Address Register ............................................... 275 7.1.28 RP6D—Root Port 6 Descriptor Register..................................................... 275 7.1.29 RP6BA—Root Port 6 Base Address Register ............................................... 275 7.1.30 ILCL— ...
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... LAN Control / Status Registers (CSR) (LAN Controller—B1:D8:F0).......................... 315 8.2.1 SCB_STA—System Control Block Status Word Register (LAN Controller—B1:D8:F0)................................................................... 316 8.2.2 SCB_CMD—System Control Block Command Word Register (LAN Controller—B1:D8:F0)....................................................... 317 8.2.3 SCB_GENPNT—System Control Block General Pointer Register (LAN Controller—B1:D8:F0)....................................................... 319 ® Intel ICH7 Family Datasheet 11 ...
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... PMSK8—Polling Mask 8 Register (ASF Controller—B1:D8:F0) ...................... 344 9 PCI-to-PCI Bridge Registers (D30:F0).................................................................... 345 9.1 PCI Configuration Registers (D30:F0) ................................................................. 345 9.1.1 VID— Vendor Identification Register (PCI-PCI—D30:F0) ............................. 346 9.1.2 DID— Device Identification Register (PCI-PCI—D30:F0) ............................. 346 9.1.3 PCICMD—PCI Command (PCI-PCI—D30:F0) ............................................. 346 12 ® Intel ICH7 Family Datasheet ...
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... I/F Generic Decode Range 1 Register (LPC I/F—D31:F0) .... 375 10.1.23GEN2_DEC—LPC I/F Generic Decode Range 2Register (LPC I/F—D31:F0)..... 375 10.1.24GEN3_DEC—LPC I/F Generic Decode Range 3Register (LPC I/F—D31:F0)..... 376 10.1.25GEN4_DEC—LPC I/F Generic Decode Range 4Register (LPC I/F—D31:F0)..... 376 10.1.26FWH_SEL1—Firmware Hub Select 1 Register (LPC I/F—D31:F0) ................. 377 ® Intel ICH7 Family Datasheet 13 ...
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... Real Time Clock Registers (LPC I/F—D31:F0)....................................................... 409 10.6.1 I/O Register Address Map (LPC I/F—D31:F0) ............................................ 409 10.6.2 Indexed Registers (LPC I/F—D31:F0) ...................................................... 410 10.6.2.1 RTC_REGA—Register A (LPC I/F—D31:F0) .................................. 411 10.6.2.2 RTC_REGB—Register B (General Configuration) (LPC I/F—D31:F0). 412 10.6.2.3 RTC_REGC—Register C (Flag Register) (LPC I/F—D31:F0) ............. 413 14 ® Intel ICH7 Family Datasheet ...
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... GPI SMI Enable Register ................... 452 10.8.3.15ALT_GP_SMI_STS—Alternate GPI SMI Status Register.................. 452 10.8.3.16GPE_CNTL— General Purpose Control Register ............................ 453 10.8.3.17DEVACT_STS — Device Activity Status Register .......................... 454 10.8.3.18SS_CNT— Intel SpeedStep Control Register (Mobile/Ultra Mobile Only) ................................ 455 10.8.3.19C3_RES— C3 Residency Register (Mobile/Ultra Mobile Only) ......... 455 10.9 System Management TCO Registers (D31:F0) ..................................................... 456 10.9.1 TCO_RLD— ...
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... SATA Controller Registers (D31:F2) (Desktop and Mobile Only) ............................. 489 12.1 PCI Configuration Registers (SATA–D31:F2)......................................................... 489 12.1.1 VID—Vendor Identification Register (SATA—D31:F2).................................. 491 12.1.2 DID—Device Identification Register (SATA—D31:F2).................................. 491 12.1.3 PCICMD—PCI Command Register (SATA–D31:F2)...................................... 491 12.1.4 PCISTS — PCI Status Register (SATA–D31:F2) .......................................... 492 16 ® Intel ICH7 Family Datasheet ...
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... Register (IDE D31:F1) .......................................................................... 497 12.1.14BAR — Legacy Bus Master Base Address Register (SATA–D31:F2) ............... 497 12.1.15ABAR — AHCI Base Address Register (SATA–D31:F2) ................................ 497 12.1.15.1Non AHCI Capable (Intel Components Only) .................................................................. 497 12.1.15.2AHCI Capable (Intel 12.1.16SVID—Subsystem Vendor Identification Register (SATA–D31:F2) ................ 498 12.1.17SID— ...
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... BMID[P,S]—Bus Master IDE Descriptor Table Pointer Register (D31:F2) ........ 522 12.2.4 AIR—AHCI Index Register (D31:F2)......................................................... 522 12.2.5 AIDR—AHCI Index Data Register (D31:F2) ............................................... 522 12.3 AHCI Registers (D31:F2) (Intel 12.3.1 AHCI Generic Host Control Registers (D31:F2).......................................... 524 12.3.1.1 CAP—Host Capabilities Register (D31:F2) ................................... 524 12.3.1.2 GHC—Global ICH7 Control Register (D31:F2) .............................. 526 12.3.1.3 IS— ...
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... EHCI Legacy Support Extended Capability Register (USB EHCI—D29:F7).................................................. 556 13.1.27LEG_EXT_CS—USB EHCI Legacy Support Extended Control / Status Register (USB EHCI—D29:F7) ......................................... 557 13.1.28SPECIAL_SMI—Intel Specific USB 2.0 SMI Register (USB EHCI—D29:F7) ..... 559 13.1.29ACCESS_CNTL—Access Control Register (USB EHCI—D29:F7) .................... 560 13.2 Memory-Mapped I/O Registers .......................................................................... 561 13.2.1 Host Controller Capability Registers ........................................................ 561 13.2.1.1 CAPLENGTH— ...
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... Bus Master IDE I/O Registers (IDE—D31:F1) ....................................................... 615 15.2.1 BMICP—Bus Master IDE Command Register (IDE—D31:F1) ........................ 615 15.2.2 BMISP—Bus Master IDE Status Register (IDE—D31:F1) ............................. 616 15.2.3 BMIDP—Bus Master IDE Descriptor Table Pointer Register (IDE—D31:F1) ..... 617 20 ® Intel ICH7 Family Datasheet ...
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... HEADTYP—Header Type Register (Modem—D30:F3) .................................. 650 17.1.10MMBAR—Modem Mixer Base Address Register (Modem—D30:F3) ................ 651 17.1.11MBAR—Modem Base Address Register (Modem—D30:F3)........................... 651 17.1.12SVID—Subsystem Vendor Identification Register (Modem—D30:F3) ............ 652 17.1.13SID—Subsystem Identification Register (Modem—D30:F3) ........................ 652 ® Intel ICH7 Family Datasheet 21 ...
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... Express—D28:F0/F1/F2/F3/F4/F5) ................................................... 672 18.1.15MBL—Memory Base and Limit Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) ................................................... 673 18.1.16PMBL—Prefetchable Memory Base and Limit Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) ................................................... 673 18.1.17PMBU32—Prefetchable Memory Base Upper 32 Bits Register (PCI Express—D28:F0/F1/F2/F3/F4/F5)....................................... 674 22 ® Intel ICH7 Family Datasheet ...
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... Status Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) ... 693 18.1.46RPDCGEN - Root Port Dynamic Clock Gating Enable (PCI Express-D28:F0/F1/F2/F3/F4/F5) (Mobile Only)................................. 694 18.1.47IPWS—Intel (PCI Express—D28:F0/F1/F2/F3/F4/F5) (Mobile Only) ............................... 694 18.1.48VCH—Virtual Channel Capability Header Register (PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 695 ® Intel ICH7 Family Datasheet ® PRO/Wireless 3945ABG Status 23 ...
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... Express—D28:F0/F1/F2/F3/F4/F5) ................................................... 704 ® 19 Intel High Definition Audio Controller Registers (D27:F0).................................... 705 ® 19.1 Intel High Definition Audio PCI Configuration Space (Intel Audio— D27:F0) .............................................................................................. 705 19.1.1 VID—Vendor Identification Register ® (Intel High Definition Audio Controller—D27:F0) ..................................... 707 19.1.2 DID—Device Identification Register ® ...
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... Message Lower Address Register ® (Intel High Definition Audio Controller—D27:F0)..................................... 718 19.1.29MMUA—MSI Message Upper Address Register ® (Intel High Definition Audio Controller—D27:F0)..................................... 718 19.1.30MMD—MSI Message Data Register ® (Intel High Definition Audio Controller—D27:F0)..................................... 719 19.1.31PXID— ...
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... Resource Status Register ® (Intel High Definition Audio Controller—D27:F0) ..................................... 726 19.1.47RCCAP—Root Complex Link Declaration Enhanced Capability Header Register (Intel Controller—D27:F0) (Desktop and Mobile Only) ........................................ 726 19.1.48ESD—Element Self Description Register ® (Intel High Definition Audio Controller—D27:F0) ..................................... 726 19.1.49L1DESC— ...
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... Descriptor Status Register ® (Intel High Definition Audio Controller—D27:F0)..................................... 752 19.2.38SDLPIB—Stream Descriptor Link Position in Buffer Register (Intel 19.2.39SDCBL—Stream Descriptor Cyclic Buffer Length Register ® (Intel High Definition Audio Controller—D27:F0)..................................... 753 19.2.40SDLVI—Stream Descriptor Last Valid Index Register ® ...
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... High Definition Audio Controller—D27:F0) ..................................... 756 19.2.44SDBDPL—Stream Descriptor Buffer Descriptor List Pointer Lower Base Address Register (Intel 19.2.45SDBDPU—Stream Descriptor Buffer Descriptor List PointerUpper Base Address Register (Intel 20 High Precision Event Timer Registers..................................................................... 759 20.1 Memory Mapped Registers ................................................................................ 759 20.1.1 GCAP_ID—General Capabilities and Identification Register.......................... 760 20.1.2 GEN_CONF— ...
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... Generation of SERR# to Platform ............................................................................. 105 5-2 64-Word EEPROM Read Instruction Waveform............................................................ 112 5-3 LPC Interface Diagram ............................................................................................ 118 5-4 LPC Bridge SERR# Generation ................................................................................. 123 ® 5-5 Intel ICH7 DMA Controller ..................................................................................... 124 5-6 DMA Request Assertion through LDRQ# .................................................................... 127 5-7 Coprocessor Error Timing Diagram ........................................................................... 151 5-8 Physical Region Descriptor Table Entry...................................................................... 186 5-9 SATA Power States ...
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... ICH7 Package (Bottom View).......................................................................... 836 ® 24-3Intel ICH7 Package (Side View).............................................................................. 836 24-4Intel ICH7-U Package Drawing ................................................................................. 837 25-1XOR Chain Test Mode Selection, Entry and Testing...................................................... 839 25-2Example XOR Chain Circuitry ................................................................................... 840 Tables 1-1 Industry Specifications ..............................................................................................39 1-2 PCI Devices and Functions .........................................................................................43 ® ...
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... Bits Reset by RTCRST# Assertion ......................................................... 148 5-22INIT# Going Active ................................................................................................ 150 5-23NMI Sources.......................................................................................................... 151 5-24DP Signal Differences ............................................................................................. 152 5-25General Power States for Systems Using Intel 5-26State Transition Rules for Intel 5-27System Power Plane ............................................................................................... 156 5-28Causes of SMI# and SCI ......................................................................................... 157 5-29Break Events (Mobile/Ultra Mobile Only).................................................................... 160 5-30Sleep Types ...
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... ICH7 Standard SPI Commands ....................................................................... 247 5-64Flash Protection Mechanism Summary....................................................................... 248 6-1 PCI Devices and Functions ....................................................................................... 254 6-2 Fixed I/O Ranges Decoded by Intel 6-3 Variable I/O Decode Ranges..................................................................................... 258 6-4 Memory Decode Ranges from Processor Perspective.................................................... 259 7-1 Chipset Configuration Register Memory Map (Memory Space) ....................................... 263 8-1 LAN Controller PCI Register Address Map (LAN Controller—B1:D8:F0) ........................... 303 8-2 Configuration of Subsystem ID and Subsystem Vendor ID via EEPROM ...
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... Interface Timings (Desktop and Mobile Only) ................................................... 810 23-17SMBus Timing...................................................................................................... 810 23-19LPC Timing .......................................................................................................... 811 23-20Miscellaneous Timings........................................................................................... 811 ® 23-18AC ’97 / Intel High Definition Audio Timing ............................................................ 811 23-21SPI Timings (Desktop and Mobile Only) ................................................................... 812 23-22(Power Sequencing and Reset Signal Timings........................................................... 812 23-23Power Management Timings .................................................................................. 814 25-1XOR Test Pattern Example ...
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... Initial release -002 • Added specificaitons for ICH7DH, ICH7-M, and ICH7-M DH • Added specifications for the ICH7-U -003 • Added Documentation Changes/Specification Changes from Spec Update Revision -020. 34 Description § Intel Date April 2005 January 2006 April 2007 ® ICH7 Family Datasheet ...
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... Integrated LAN Controller (Desktop and Mobile Only) — Integrated ASF Management Controller — Supports IEEE 802.3 — LAN Connect Interface (LCI) — 10/100 Mb/s Ethernet Support NEW: Intel Active Management Technology (Desktop and Mobile Only) ® NEW: Intel Quick Resume Technology Support (Digital ...
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... New: Package mm, 452 balls (Ultra Mobile only) DMI (To (G)MCH) USB 2.0 (Supports 8 USB ports) IDE SATA (4 ports) ® Intel ICH7 AC ’97/Intel® High Definition Audio Codec(s) PCI Express* x1 LAN Connect GPIO LPC I/F Other ASICs Super I/O (Optional) TPM Firmware Hub ...
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... Ultra Mobile Configuration ® Intel ICH7 Family Datasheet DMI (To (G)MCH) USB 2.0 (Supports 8 USB ports) IDE SATA (2 ports) ® Intel ICH7-M AC’97/Intel® High Definition Audio Codec(s) PCI Bus PCI Express x1 LAN Connect GPIO LPC I/F Other ASICs (Optional) Super I/O TPM (Optional) ...
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... Intel ICH7 Family Datasheet ...
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... ICH7-U Ultra Mobile component. This datasheet assumes a working knowledge of the vocabulary and principles of PCI Express*, USB, IDE, AHCI, SATA, Intel AC ’97, SMBus, PCI, ACPI and LPC. Although some details of these features are described within this manual, refer to the individual industry specifications listed in Table 1-1 for the complete details ...
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... ICH7 interface signals and a detailed description of each signal. Signals are arranged according to interface and details are provided as to the drive characteristics (Input/Output, Open Drain, etc.) of all signals. Chapter 3. Intel Chapter 3 provides a complete list of signals, their associated power well, their logic level in each suspend state, and their logic level before and after reset ...
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... AC-link to the codec where the registers reside. Chapter 18. Intel Chapter 18 provides a detailed description of all registers that reside in the Intel Definition Audio controller. This controller resides at Device 27, Function 0 (D27:F0). Chapter 19. PCI Express* Port Controller Registers Chapter 19 provides a detailed description of all registers that reside in the PCI Express controller ...
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... Supports Audio Codec ’97, Revision 2.3 Specification (a.k.a., AC ’97 Component Specification, Revision 2.3) which provides a link for Audio and Telephony codecs ( channels) (Desktop and Mobile Only) • Supports Intel High Definition Audio • Supports Intel • Supports Intel • Low Pin Count (LPC) interface • ...
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... PCI Express Port 3 (Desktop and Mobile Only) PCI Express Port 4 (Desktop and Mobile Only) ® PCI Express Port 5 (Intel ICH7R, ICH7DH, and ICH7-M DH Only) PCI Express Port 6 (Intel ICH7R, ICH7DH, and ICH7-M DH Only) ® Intel High Definition Audio Controller LAN Controller (Desktop and Mobile Only) Table 1-2 ...
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... Intel Matrix Storage Technology (Intel DH Only) The ICH7 provides support for Intel Matrix Storage Technology, providing both AHCI (see above for details on AHCI) and integrated RAID functionality. The industry-leading RAID capability provides high-performance RAID and 10 functionality (RAID 0/1 functionality for ICH7-M DH SATA ports of ICH7. Matrix RAID support is provided to allow multiple RAID levels to be combined on a single set of hard drives, such as RAID 0 and RAID 1 on two disks ...
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... Advanced Programmable Interrupt Controller (APIC) In addition to the standard ISA compatible Programmable Interrupt controller (PIC) described in the previous section, the ICH7 incorporates the Advanced Programmable Interrupt Controller (APIC). ® Intel ICH7 Family Datasheet for details). 45 ...
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... BIOS and sensors on the motherboard to a remote server running a management console. The controller can also be programmed to accept commands back from the management console and execute those commands on the local system. 46 for details. Introduction Section 5.19 ® Intel ICH7 Family Datasheet ...
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... Intel Active Management Technology (Intel Mobile Only) Intel Active Management Technology is the next generation of client manageability via the wired network. Intel AMT is a set of advanced manageability features developed as a direct result of IT customer feedback gained through Intel market research. ® Intel ICH7 Family Datasheet ® ...
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... ICH7 to generate either an SMI#, NMI, SERR#, or TCO interrupt. • Function Disable. The ICH7 provides the ability to disable the following integrated functions: AC ’97 Modem, AC ’97 Audio, IDE, LAN, USB, LPC, Intel HD Audio, SATA, or SMBus. Once disabled, these functions no longer decode I/O, memory, or PCI configuration space ...
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... The ICH7 Intel HD Audio digital link shares pins with the AC-link. Concurrent operation of Intel HD Audio and AC ’97 functionality is not supported. The ICH7 Intel HD Audio controller supports codecs. With the support of multi-channel audio stream, 32-bit sample depth, and sample rate up to 192 kHz, the Intel levels of audio experience ...
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... Yes / Yes Short Base AHCI Name Features ICH7-M Yes Yes ICH7-M DH Yes Yes Not all ICH7-U No features § Introduction ® Intel ® 6 PCI Intel Quick Express AMT Resume Ports Support Technology 2 No Yes No 2 Yes Yes Yes 2 Yes Yes No 1 ® ...
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... Signal Description 2 Signal Description This chapter provides a detailed description of each signal. The signals are arranged in functional groups according to their associated interface. interface signals for the Intel ICH7DH. Figure 2-2 82801GHM ICH7-M DH. U. The “#” symbol at the end of the signal name indicates that the active, or asserted state occurs when the signal low voltage level. When “ ...
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... DMI[3:0]TXP, DMI[3:0]TXN DMI[3:0]RXP, DMI[3:0]RXN DMI_ZCOMP DMI_IRCOMP FWH[3:0] / LAD[3:0] FWH[4] / LFRAME# LAD[3:0] / FWH[3:0] LFRAME# / FWH[4] LDRQ[0]# LDRQ[1]# / GPIO[23] SMBDATA SMBCLK SMBALERT# / GPIO[11] INTRUDER# SMLINK[1:0] LINKALERT# LAN_CLK LAN_RXD[2:0] LAN_TXD[2:0] LAN_RSTSYNC Digital EL_RSVD / GPIO26 Home EL_STATE[1:0] / GPIO[28:27] Only ® Intel ICH7 Family Datasheet ...
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... IGNNE# INIT# Power INIT3_3# Mgnt. Processor INTR NMI Interface SMI# STPCLK# RCIN# A20GATE DPSLP# SERIRQ Interrupt PIRQ[D:A]# Interface AC '97/ IDEIRQ ® Intel USBP[7:0]P Definition USBP[7:0]N Audio OC[4:0]# USB Direct Media Interface USBRBIAS USBRBIAS# Firmware Hub RTCX1 RTC RTCX2 LPC CLK14 Interface CLK48 ...
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... ACZ_RST#, ACZ_SYNC, ACZ_SDOUT High ACZ_SDIN[2:0] ACZ_BIT_CLK DMI[1:0]TXP, DMI[1:0]TXN DMI[1:0]RXP, DMI[1:0]RXN DMI_ZCOMP DMI_IRCOMP FWH[3:0] / LAD[3:0] FWH[4] / LFRAME# LAD[3:0] / FWH[3:0] LFRAME# / FWH[4] LDRQ0# LDRQ1# / GPIO[23] SMBDATA SMBCLK SMBALERT# / GPIO[11] INTRUDER# LINKALERT# ICH7 Signals Ultra Mobile ® Intel ICH7 Family Datasheet ...
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... ICH7DH/ICH7-M DH Only) PERp[1:4], PERn[5:6] (ICH7R/ICH7DH/ ICH7-M DH Only) ® Intel ICH7 Family Datasheet Description Direct Media Interface Differential Transmit Pair 0:3 Direct Media Interface Differential Receive Pair 0:3 Impedance Compensation Input: Determines DMI input impedance. Impedance/Current Compensation Output: Determines DMI output impedance and bias current. ...
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... EEPROM Chip Select: This is the chip select signal to the EEPROM. Description Firmware Hub Signals: These signals are multiplexed with the LPC address signals. Firmware Hub Signals: This signal is multiplexed with the LPC LFRAME# signal. Signal Description ® Intel ICH7 Family Datasheet ...
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... During the first clock of a transaction, AD[31:0] contain a physical address (32 bits). During subsequent clocks, AD[31:0] contain data. The ® Intel ICH7 will drive all 0s on AD[31:0] during the address phase of all PCI Special Cycles. Bus Command and Byte Enables: The command and byte enable signals are multiplexed on the same PCI pins ...
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... PCIRST Description Target Ready: TRDY# indicates the Intel complete the current data phase of the transaction. TRDY# is used in conjunction with IRDY#. A data phase is completed when both TRDY# and IRDY# are sampled asserted. During a read, TRDY# indicates that the ICH7 target, has placed valid data on AD[31:0]. During a write, TRDY# indicates the ICH7 target is prepared to latch data ...
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... SATA3RXP SATA3RXN (Desktop Only) SATARBIAS SATARBIAS# ® Intel ICH7 Family Datasheet Description PCI Lock: This signal indicates an exclusive bus operation and may require multiple transactions to complete. The ICH7 asserts PLOCK# when it performs non-exclusive transactions on the PCI bus. PLOCK# is ignored when PCI masters are granted the bus in desktop configurations ...
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... IDE connector. They are used to indicate O which byte in either the ATA command block or control block is being addressed. IDE Device Data: These signals directly drive the corresponding signals on the IDE connector. There is a weak internal pull-down resistor on DD7. Signal Description Description ® Intel ICH7 Family Datasheet ...
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... IDE function and are not associated with any AT compatible DMA channel. There is a weak internal pull-down resistor on this signal. IDE Device DMA Acknowledge: This signal directly drives the DAK# signal on the IDE connector. DDACK# is asserted by the Intel indicate to IDE DMA slave devices that a given data transfer cycle O (assertion of DIOR# or DIOW DMA data transfer cycle ...
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... PIRQE# is connected to IRQ20, PIRQF# to IRQ21, PIRQG# to IRQ22, and PIRQH# to IRQ23. This frees the legacy interrupts. If not needed for interrupts, these signals can be used as GPIO. IDE Interrupt Request: This interrupt input is connected to the IDE drive. Signal Description ® Intel ICH7 Family Datasheet ...
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... These ports can be routed to UHCI controller #1 or the EHCI controller. I/O NOTE: No external resistors are required on these signals. The ® Intel ICH7 integrates 15 kΩ pull-downs and provides an output driver impedance of 45 Ω which requires no external series resistor Universal Serial Bus Port [3:2] Differential: These differential pairs are used to transmit data/address/command signals for ports 2 and 3 ...
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... Mobile Only) 64 Description ® Platform Reset: The Intel ICH7 asserts PLTRST# to reset devices on the platform (e.g., SIO, FWH, LAN, (G)MCH, IDE, TPM, etc.). The ICH7 asserts PLTRST# during power-up and when S/W initiates a hard reset sequence through the Reset Control register (I/O Register CF9h) ...
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... STP_PCI# (Mobile/Ultra Mobile Only) / GPIO18 (Desktop Only) ® Intel ICH7 Family Datasheet Description System Reset: This pin forces an internal reset after being debounced. The ICH7 will reset immediately if the SMBus is idle; I otherwise, it will wait ± for the SMBus to idle before forcing a reset on the system ...
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... CPU Sleep: This signal puts the processor into a state that saves substantial power compared to Stop-Grant state. However, during that ® time, no snoops occur. The Intel signal when going to the S1 state. (Desktop Only) Reserved. (Mobile/Ultra Mobile Only) Numeric Coprocessor Error: This signal is tied to the coprocessor error signal on the processor ...
Page 67
... O STPCLK# O RCIN# I ® Intel ICH7 Family Datasheet Description Ignore Numeric Error: This signal is connected to the ignore error pin on the processor. IGNNE# is only used if the ICH7 coprocessor error reporting function is enabled in the OIC.CEN register (Chipset Config Registers:Offset 31FFh: bit 1). If FERR# is active, indicating a coprocessor error, a write to the Coprocessor Error register (I/O register F0h) causes the IGNNE asserted ...
Page 68
... SMLINK1 corresponds to an SMBus Data signal. SMLink Alert: This signal is an output of the integrated LAN and input to either the integrated ASF or an external management controller in order for the LAN’s SMLINK slave to be serviced. Signal Description Description ® Intel ICH7 Family Datasheet ...
Page 69
... Mobile Only) DMI_CLKP, I DMI_CLKN ® Intel ICH7 Family Datasheet Description Crystal Input 1: This signal is connected to the 32.768 kHz crystal external crystal is used, RTCX1 can be driven with the desired clock rate. Crystal Input 2: This signal is connected to the 32.768 kHz crystal external crystal is used, RTCX2 should be left floating ...
Page 70
... Test Point 0: This signal must have an external pull-up to VccSus3_3. Test Point 1: Route signal to a test point. Test Point 2: Route signal to a test point. Test Point 3: Route signal to a test point. Signal Description for more details. There is a weak ® Intel ICH7 Family Datasheet ...
Page 71
... Intel High Definition Audio mode is selected through D30:F1:40h, bit 0: AZ/AC97#. This bit selects the mode of the shared Intel High Definition Audio/AC ‘97 signals. When set ‘97 mode is selected. When set to 1 Intel High Definition Audio mode is selected. The bit defaults to 0 (AC ‘97 mode). ...
Page 72
... MHz. Type ® Intel Quick Resume Technology Reserved: This signal is reserved and should be left connect when Intel Quick Resume Technology is enabled. I/O NOTE: This signal cannot be reused as a GPIO when Intel Quick Resume Technology is enabled. ...
Page 73
... ICH7DH Only: Multiplexed with EL_STATE1 ® Intel ICH7, ICH7R, and Mobile Only: Unmultiplexed. ICH7DH Only: Multiplexed with EL_STATE0 ® Intel ICH7, ICH7R, and Mobile Only: Unmultiplexed. ICH7DH Only: Multiplexed with EL_RSVD Unmultiplexed. Unmultiplexed. Not cleared by CF9h reset event. Multiplexed with LDRQ1# Multiplexed with REQ4# Multiplexed with SATA0GP ...
Page 74
... Some ICH7 GPIOs may be connected to pins on devices that exist in the core well. If these GPIOs are outputs, there is a danger that a loss of core power (PWROK low Power Button Override event will result in the Intel ICH7 driving a pin to a logic 1 to another device that is powered down. 2.23 Power and Ground Table 2-22 ...
Page 75
... Mobile configurations. Mobile Only) NOTE: In Desktop mode this signal is added to the VccSus3_3 group. This pin provides the core supply for Intel High Definition Audio (1 pin). This pin VccHDA can be either 1 3.3 V. This power may be shut off in S3, S4 (Mobile/Ultra states ...
Page 76
... Port Config EE_CS (Desktop Reserved and Mobile Only) 76 Description pull VccRTC low. Clearing CMOS in an Intel done by using a jumper on RTCRST# or GPI. 2-13. When Sampled Allows entrance to XOR Chain testing when TP3 pulled low at rising edge of PWROK. See for XOR Chain functionality information. ...
Page 77
... NOTE: This signal should not be pulled low. The signal has a weak internal pull-up. If the signal is sampled low, this indicates that the system is strapped to the “top-block swap” mode (Intel ICH7 inverts A16 for all cycles targeting FWH BIOS Rising Edge of space). The status of this strap is readable via the ...
Page 78
... Diodes (20% tolerance) 20 KΩ 32.768 kHz Xtal 1 µ (5% tolerance) § Signal Description Comment for functionality information. for functionality information. This Figure 2-4 shows an VCCRTC RTCX2 R1 10 MΩ RTCX1 (5% tolerance) RTCRST# ® Intel ICH7 Family Datasheet ...
Page 79
... ACZ_BIT_CLK, Intel Audio ACZ_RST#, Intel High Definition Audio ACZ_SDIN[2:0], Intel High Definition Audio ACZ_SDOUT, Intel High Definition Audio ACZ_SYNC, Intel High Definition Audio DD7 DDREQ DPRSLPVR / GPIO16 EE_CS (Desktop and Mobile Only) EE_DIN (Desktop and Mobile Only) EE_DOUT (Desktop and Mobile Only) ...
Page 80
... Both Function 2 and Function 3 of Device 30 are disabled. Otherwise, the integrated Pull-down resistor is disabled. 2. The AC ‘97/Intel High Definition Audio Link signals may either all be configured AC-Link or an Intel High Definition Audio Link. 3. Simulation data shows that these resistor values can range from 10 kΩ kΩ. ...
Page 81
... ICH7R and ICH7DH Only) DMI[3:0]TXP, DMI[3:0]TXN ® Intel ICH7 Family Datasheet show the power plane associated with the output and I/O Tri-state. ICH7 not driving the signal high or low. ICH7 is driving the signal to a logic 1 ICH7 is driving the signal to a logic 0 ...
Page 82
... Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Undefined Off Off High Off Off High-Z Off Off Low Off Off High Off Off High Off Off Defined Off Off Defined Off Off ® Intel ICH7 Family Datasheet ...
Page 83
... USBP[7:0][P,N] USBRBIAS OC[7:5]# / GPIO[31:29] PLTRST# SLP_S3# SLP_S4# SLP_S5# SUS_STAT# SUSCLK A20M# CPUPWRGD / GPIO49 CPUSLP# IGNNE# INIT# INIT3_3V# INTR NMI SMI# ® Intel ICH7 Family Datasheet Immediately During Power after 1 PLTRST# / Plane PLTRST# 2 RSMRST# RSMRST# Core High-Z High-Z Core Input Input Core Low ...
Page 84
... Core Internal Pull- Low down AC ’97 Interface Suspend Low Low Core Low Running Core Low Running Intel ® High Definition Audio Interface Suspend Low Low High-Z with Core Internal Pull- Running down High-Z with Core Internal Pull- Running down High-Z with ...
Page 85
... High-Z. 8. ICH7 drives these signals Low before PWROK rising and Low after the processor Reset. 9. Low until Intel High Definition Audio Controller Reset bit set (D27:F0:Offset HDBAR+08h:bit 0), at which time ACZ_RST# will be High and ACZ_BIT_CLK will be Running. 10. ...
Page 86
... Off Off High-Z Off Off High Off Off High Off Off Defined Note 5 Note 5 Defined Note 5 Note 5 Defined Note 5 Note 5 Defined Note 5 Note 5 Defined Note 5 Note 5 Undefine Off Off d d High Off Off High-Z Off Off ® Intel ICH7 Family Datasheet ...
Page 87
... Suspend GPIO[31:29] PLTRST# Suspend SLP_S3# Suspend SLP_S4# Suspend SLP_S5# Suspend STP_PCI# Core STP_CPU# Core SUS_STAT# Suspend DPRSLPVR Core DPRSTP# Core SUSCLK Suspend ® Intel ICH7 Family Datasheet Immediately During after 1 PLTRST# / C3/C4 1 PLTRST RSMRST# 2 RSMRST# Low Low Defined High High High High ...
Page 88
... Off Define Defined Defined d Define Defined Defined d Define Defined Defined d Defined Off Off Cold High Reset Bit Low Low (High) Low Off Off Low Off Off High TBD Low Low Low Off Off Low Off Off ® Intel ICH7 Family Datasheet ...
Page 89
... ICH7 drives these signals High after the processor Reset. 9. CPUPWRGD is an output that represents a logical AND of the Intel and PWROK signals, and thus will be driven low by ICH7 when either VRMPWRGD or PWROK are inactive. During boot, or during a hard reset with power cycling, CPUPWRGD will be expected to transition from low to High ...
Page 90
... Low until Intel High Definition Audio Controller Reset bit set (D27:F0:Offset HDBAR+08h:bit 0), at which time ACZ_RST# will be High and ACZ_BIT_CLK will be Running. 12. GPIO18 will toggle at a frequency of approximately 1 Hz when the ICH7 comes out of reset 13. GPIO25 transitions from pulled high internally to actively driven within 100 ms of the deassertion of the RSMRST# pin ...
Page 91
... SATA[3:0]RXN SATARBIAS# SATA[3:0] GPIO[31:29,26] SERR# 2 SMBALERT# / GPIO11 SYS_RESET# THRM# THRMTRIP# TP0 TP3 USBRBIAS# VRMPWRGD ® Intel ICH7 Family Datasheet Power Well Driver During Reset External Pull-up or RTC Pull-down Core IDE Device LAN Connect Suspend Component Suspend External RC Circuit LAN Connect Suspend ...
Page 92
... Driven Static Low Low Running Running Low Low Driven Driven Note 2 Note 2 Static Static Low Low Driven Driven Driven Driven Driven Driven Low Low Driven Static Low Low Driven Driven Driven Driven Driven Driven Driven Driven ® Intel ICH7 Family Datasheet ...
Page 93
... SATA[2]RXN (Mobile Only) SATARBIAS# (Mobile Only) SATA[2,0]GP (Mobile Only) SERR# SMBALERT# / Suspend 3 GPIO11 SYS_RESET# Suspend THRM# ® Intel ICH7 Family Datasheet Driver During Reset Well Core IDE Device LAN Connect LAN Component Power Supply LAN Connect LAN Component Core LPC Devices ...
Page 94
... signal states are platform implementation specific, as some external components HOT and interfaces may be powered when the Intel 2. LAN Connect and EEPROM signals will either be “Driven” or “Low” in S3–S5 states depending upon whether or not the LAN power planes are active. ...
Page 95
... Mobile only) LAN_CLK (Desktop and MHz Mobile only) SPI_CLK (Desktop and Mobile Only) ® Intel ICH7 Family Datasheet ICH7 and System Clock Figure 4-1 Source Main Clock 100 MHz Differential clock pair used for SATA. Generator Main Clock 100 MHz Differential clock pair used for DMI ...
Page 96
... Gen. 14.31818 MHz 48.000 MHz PCI Express Differential 100 MHz Clock Fan Out Dev ice Diff. Pairs PCI Clocks (33 MHz) 14.31818 MHz 48 MHz PCI Express Differential 100 MHz Clock Fan Diff. Pairs Out Device ® Intel ICH7 Family Datasheet ...
Page 97
... Intel ICH7 and System Clock Domains Figure 4-3. Ultra Mobile Only Conceptual Clock Diagram ® Intel ICH7-U 32 kHz XTAL ® Intel ICH7 Family Datasheet 33 MHz 14.31818 MHz 48.000 MHz Clock Generator STP_CPU# STP_PCI# DMI 100 MHz Diff Pair 24 MHz High Definition Audio Codec(s) SUSCLK# (32 kHz) § ...
Page 98
... Intel ICH7 and System Clock Domains ® Intel ICH7 Family Datasheet ...
Page 99
... PCI Bridge Initiator Cycle Types Command I/O Read/Write Memory Read/Write Configuration Read/Write Special Cycles 5.1.2.1 Memory Reads and Writes The bridge bursts memory writes on PCI that are received as a single packet from DMI. ® Intel ICH7 Family Datasheet C/BE# Notes 2h/3h Non-posted 6h/7h Writes are posted Ah/Bh Non-posted ...
Page 100
... FRAME# at the next legal clock edge when there is another active request to use the PCI bus. 5.1.2.7 Dual Address Cycle (DAC) The bridge will issue full 64-bit dual address cycles for device memory-mapped registers above 4 GB. 100 Functional Description ® Intel ICH7 Family Datasheet ...
Page 101
... The PCIRST# pin is generated under two conditions: • PLTRST# active • BCTRL.SBR (D30:F0:Offset 3Eh:bit 6) set to 1 The PCIRST# pin is in the resume well. PCIRST# should be tied to PCI bus agents, but not other agents in the system. ® Intel ICH7 Family Datasheet 101 ...
Page 102
... PCI ranges do not conflict with graphics aperture ranges in the Host controller. Note: All downstream devices should be disabled before reconfiguring the PCI Bridge. Failure may cause undefined results. 102 Functional Description Definition ® Intel ICH7 Family Datasheet ...
Page 103
... When accessing Device 1, the ICH7 asserts AD17. This mapping continues all the way up to device 15 where the ICH7 asserts AD31. Note that the ICH7’s internal functions (AC ’97 on Desktop/Mobile, Intel High Definition Audio, IDE, USB, SATA on Desktop/ Mobile and PCI Bridge) are enumerated like they are off of a separate PCI bus (DMI) from the external PCI bus. The integrated LAN controller (Desktop and Mobile Only) is Device 8 on the ICH7’ ...
Page 104
... RSTS.RID (D28:F0/F1/F2/F3/F4/F5:Offset 60h:bits 15:0 interrupt is enabled via 104 Interrupt Register Functional Description Wire- MSI Action Mode Action Wire inactive No action Send Wire active message Send Wire active message Send Wire active message Wire inactive No action Send Wire active message . When a device HOT ® Intel ICH7 Family Datasheet ...
Page 105
... PCI header, or through PCI Express mechanisms involving bits in the PCI Express capability structure. Figure 5-1. Generation of SERR# to Platform Secondary Parity Error PCI Primary Parity Error Secondary SERR# PCI Express ® Intel ICH7 Family Datasheet Section 5.2.2.4 for SMI/SCI generation. PCICMD.SEE Correctable SERR# Fatal SERR# Non-Fatal SERR# PSTS.SSE SERR# ...
Page 106
... A single write to the Slot Control register is considered single command, and hence receives a single command complete, even if the write affects more than one field in the Slot Control Register. 106 Functional Description ® Intel ICH7 Family Datasheet ...
Page 107
... Link Active State Changed - SMSCS.HPLAS (D28:F0/F1/F2/F3/F4/F5:Offset DCh:bit 4) When any of these bits are set, SMI # will be generated. These bits are set regardless of whether interrupts or SCI is enabled for Hot-Plug events. The SMI# may occur concurrently with an interrupt or SCI. ® Intel ICH7 Family Datasheet 107 ...
Page 108
... Deep power-down mode support • Backward compatible software with 82550, 82557, 82558 and 82559 • TCP/UDP checksum off load capabilities • Support for Intel’s Adaptive Technology 5.3.1 LAN Controller PCI Bus Interface As a Fast Ethernet controller, the role of the ICH7 integrated LAN controller is to access transmitted data or deposit received data ...
Page 109
... The LAN controller does not attempt to terminate a cycle in which a parity error was detected. This gives the initiator the option of recovery. Target-Disconnect: The LAN controller prematurely terminate a cycle in the following cases: • After accesses to its CSR • After accesses to the configuration space ® Intel ICH7 Family Datasheet 109 ...
Page 110
... CLKRUN# Signal (Mobile Only) ® The Intel ICH7 receives a free-running 33 MHz clock. It does not stop based on the CLKRUN# signal and protocol. When the LAN controller runs cycles on the PCI bus, the ICH7 makes sure that the STP_PCI# signal is high indicating that the PCI clock will be running ...
Page 111
... The LAN controller reports a PME link status event in all power states. If the Wake on LAN bit in the EEPROM is not set, the PME# signal is gated by the PME Enable bit in the PMCSR and the CSMA Configure command. ® Intel ICH7 Family Datasheet 111 ...
Page 112
... EE_DOUT The LAN controller performs an automatic read of seven words (0h, 1h, 2h, Ah, Bh, Ch, and Dh) of the EEPROM after the deassertion of Reset. 112 Figure 5- READ OP code Functional Description ® Intel ICH7 Family Datasheet ...
Page 113
... LAN Connect component, and are described in detail in the platform LAN Connect component’s datasheet. The processor writes commands to this register and the LAN controller reads or writes the control/status parameters to the platform LAN Connect component through the MDI register. ® Intel ICH7 Family Datasheet 113 ...
Page 114
... TCO packet, the ICH7 increments its nominal Receive statistic counters as well as the Receive TCO counter. 114 TCO Controller Functionality Transmit Set Receive TCO Packets Receive TCO Packets ® Read Intel ICH7 status (PM & Link state) Force TCO Mode D0 functionality plus: Read PHY registers Dx functionality plus: Configuration commands Read/Write PHY registers Section 8 ...
Page 115
... Eventually, the ICH7 increments the receive TCO static counter, clears the TCO request bit, and resumes normal control. ® Read Intel ICH7 Status (PM and Link State) The TCO controller is capable of reading the ICH7 power state and link status. Following a status change, the ICH7 asserts LINKALERT# and then the TCO can read its new power state ...
Page 116
... Remote Control — Presence Ping Response — Configurable Boot Options — Capabilities Reporting — Auto-ARP Support — System Remote Control - Power-Down - Power-Up - Power Cycle - System Reset — State-Based Security – Conditional Action on WatchDog Expire 116 Functional Description ® Intel ICH7 Family Datasheet ...
Page 117
... SMBus. However, ASF is restricted by the number of total events which may reduce the number of SMBus devices supported. The maximum number of events supported by ASF is 128. The ASF sensors are expected to operate as defined in the Alert Standard Format (ASF) Specification, Version 1.03. ® Intel ICH7 Family Datasheet 117 ...
Page 118
... Note: Contact your Intel Field Representative for the Client ASF Software Development Kit (SDK) that includes additional documentation and a copy of the client ASF software drivers. Intel also provides an ASF Console SDK to add ASF support to a management console. 5.5 LPC Bridge (w/ System and Management ...
Page 119
... NOTE: All other encodings are RESERVED. ® Intel ICH7 Family Datasheet Comment ® 1 byte only. Intel ICH7 breaks up 16- and 32-bit processor cycles into multiple 8-bit transfers. 1 byte only. ICH7 breaks up 16- and 32-bit processor cycles into multiple 8-bit transfers. Can bytes Can bytes Can bytes ...
Page 120
... Bits[1:0] are encoded as listed in Table 5-8. Transfer Size Bit Definition Bits[1:0] 00 8-bit transfer (1 byte) 01 16-bit transfer (2 bytes) Reserved. The Intel 10 running a bus master cycle drives this combination, the ICH7 may abort the transfer. 11 32-bit transfer (4 bytes) 120 shows the valid bit encodings. ...
Page 121
... DMA request deassertion and no more transfers desired for that channel. Short Wait: Part indicating wait-states. For bus master cycles, the Intel 0101 does not use this encoding. Instead, the ICH7 uses the Long Wait encoding (see next encoding below) ...
Page 122
... The ICH7 asserts both SUS_STAT# (connects to LPCPD#) and PLTRST# (connects to LRST#) at the same time when the core logic is reset (via CF9h, PWROK, or SYS_RESET#, etc.). This is not inconsistent with the LPC LPCPD# protocol. 122 Functional Description ® Intel ICH7 Family Datasheet ...
Page 123
... Functional Description 5.5.1.12 Configuration and Intel LPC Interface Decoders To allow the I/O cycles and memory mapped cycles the LPC interface, the ICH7 includes several decoders. During configuration, the ICH7 must be programmed with the same decode ranges as the peripheral. The decoders are programmed via the Device 31:Function 0 configuration space ...
Page 124
... DMA service can be presented through each channel's DMA Request Register. A software request is subject to the same prioritization as any hardware request. See the detailed register description for Request Register programming information in 124 (Figure 5-5). DMA controller 1 (DMA-1) Channel 4 Channel 5 DMA-1 DMA-2 Channel 6 Channel 7 Section 10.2. Functional Description ® Intel ICH7 Family Datasheet ...
Page 125
... Address Increment/Decrement” indicates the number added to or taken from the Current Address register after each DMA transfer cycle. The DMA Channel Mode Register determines if the Current Address Register will be incremented or decremented. ® Intel ICH7 Family Datasheet 125 ...
Page 126
... They do not depend on any specific bit pattern on the data bus. 126 Current Byte/Word Count Register Bytes Words Table 5-11. 16-Bit I/O Programmed 8-Bit I/O Programmed Address (Ch 5–7) Address (Ch 0–3) A0 A[16:1] A[23:17] Intel Functional Description Current Address Increment/ Decrement 1 1 (Shifted) 0 A[15:0] A[23:17] ® ICH7 Family Datasheet ...
Page 127
... There may be some special cases where the peripheral desires to abandon a DMA transfer. The most likely case of this occurring is due to a floppy disk controller which has overrun or underrun its FIFO, or software stopping a device prematurely. ® Intel ICH7 Family Datasheet Figure Start MSB ...
Page 128
... DMA write, where the peripheral is transferring data to main memory. The indication from the host is the same as a DMA write, so the peripheral will be driving data onto the LPC interface. However, the host will not transfer this data into main memory. 128 Functional Description ® Intel ICH7 Family Datasheet ...
Page 129
... SYNC field. This is needed to allow the 8237, that typically runs off a much slower internal clock, to see a message deasserted before it is re-asserted so that it can arbitrate to the next agent. ® Intel ICH7 Family Datasheet SIZE etc. combination to initiate another transfer to the – ...
Page 130
... This counter provides the speaker tone and is typically programmed for Mode 3 operation. The counter provides a speaker frequency equal to the counter clock frequency (1.193 MHz) divided by the initial count value. The speaker must be enabled by a write to port 061h (see NMI Status and Control ports). 130 Functional Description ® Intel ICH7 Family Datasheet ...
Page 131
... Square wave output 4 Software triggered strobe 5 Hardware triggered strobe ® Intel ICH7 Family Datasheet Function Output is 0. When count goes to 0, output goes to 1 and stays at 1 until counter is reprogrammed. Output is 0. When count goes to 0, output goes to 1 for one clock time. ...
Page 132
... The Read Back command may additionally be used to latch status information of selected counters. The status of a counter is accessed by a read from that counter's I/O port address. If multiple counter status latch operations are performed without reading the status, all but the first are ignored. 132 Functional Description ® Intel ICH7 Family Datasheet ...
Page 133
... Slave The ICH7 cascades the slave controller onto the master controller through master controller interrupt input 2. This means there are only 15 possible interrupts for the ICH7 PIC. ® Intel ICH7 Family Datasheet 7. – Typical Interrupt Connected Pin / Function Source Internal ...
Page 134
... Table 5-15. Content of Interrupt Vector Byte Master, Slave Interrupt IRQ7,15 IRQ6,14 IRQ5,13 IRQ4,12 IRQ3,11 IRQ2,10 IRQ1,9 IRQ0,8 134 Table 5-14 defines the IRR, ISR, and IMR. Description Bits [7:3] Bits [2:0] 111 110 101 100 ICW2[7:3] 011 010 001 000 Intel Functional Description ® ICH7 Family Datasheet ...
Page 135
... Following initialization, an interrupt request (IRQ) input must make a low-to-high transition to generate an interrupt. 2. The Interrupt Mask Register is cleared. 3. IRQ7 input is assigned priority 7. 4. The slave mode address is set Special mask mode is cleared and Status Read is set to IRR. ® Intel ICH7 Family Datasheet 135 ...
Page 136
... ICW4 The final write in the sequence (ICW4) must be programmed for both controllers. At the very least, bit 0 must be set indicate that the controllers are operating in an Intel Architecture-based system. 5.9.3 Operation Command Words (OCW) These command words reprogram the Interrupt controller to operate in various interrupt modes. • ...
Page 137
... ISR bit if there is a request, and reads the priority level. Interrupts are frozen from the OCW3 write to the I/O read. The byte returned during the I/O read contains bit 7 if there is an interrupt, and the binary code of the highest priority level in bits 2:0. ® Intel ICH7 Family Datasheet 137 ...
Page 138
... From a system standpoint, this mode should be used only when a nested multi-level interrupt structure is not required within a single PIC. The AEOI mode can only be used in the master controller and not the slave controller. 138 Functional Description ® Intel ICH7 Family Datasheet ...
Page 139
... PCI interrupts. Internal sources of the PIRQs, including SCI and TCO interrupts, cause the external PIRQ to be asserted. The ICH7 receives the PIRQ input, like all of the other external sources, and routes it accordingly. ® Intel ICH7 Family Datasheet 139 ...
Page 140
... HPET #2, Option for SCI, TCO No Yes No No FERR# logic IDEIRQ (legacy mode, non-combined or 3 Yes Yes combined mapped as primary), SATA Primary (legacy mode) IDEIRQ (legacy mode — combined, mapped as Yes Yes secondary), SATA Secondary (legacy mode) Functional Description Internal Modules 2 ® Intel ICH7 Family Datasheet ...
Page 141
... The address and data formats are described below in Section Note: FSB Interrupt Delivery compatibility with processor clock control depends on the processor, not the ICH7. ® Intel ICH7 Family Datasheet Direct Via PCI from Pin Message PIRQA# Internal devices are routable ...
Page 142
... Redirection Hint bit and the Destination Mode bit are both set to 1, then the logical 2 destination mode is used, and the redirection is limited only to those processors that are part of the logical group as based on the logical ID. 1:0 Will always be 00. 142 Functional Description Table 5-17 and Table 5-18 for the address and Description ® Intel ICH7 Family Datasheet ...
Page 143
... The serial IRQ protocol has two modes of operation which affect the start frame. These two modes are: Continuous, where the ICH7 is solely responsible for generating the start frame; and Quiet, where a serial IRQ peripheral is responsible for beginning the start frame. ® Intel ICH7 Family Datasheet Description 143 ...
Page 144
... The ICH7 ignores the state of these interrupts in the serial stream, and does not adjust their level based on the level seen in the serial stream. 144 Next Mode Quiet Mode. Any SERIRQ device may initiate a Start Frame Continuous Mode. Only the host (Intel Frame Functional Description 1 and IRQ2 15 frames – ...
Page 145
... IRQ13 15 IRQ14 16 IRQ15 17 IOCHCK# 18 PCI INTA# 19 PCI INTB# 20 PCI INTC# 21 PCI INTD# ® Intel ICH7 Family Datasheet Clocks Past Start Frame Ignored. IRQ0 can only be generated via the internal 2 8524 5 8 Causes SMI# if low. Will set the SERIRQ_SMI_STS bit Ignored ...
Page 146
... To ensure proper operation when adjusting the time, the new time and data values should be set at least two seconds before one of these conditions (leap year, daylight savings time adjustments) occurs. 146 Functional Description 9) are – ® Intel ICH7 Family Datasheet ...
Page 147
... RTCRST# is asserted. This RTCRST# jumper technique allows the jumper to be moved and then replaced—all while the system is powered off. Then, once booted, the RTC_PWR_STS can be detected in the set state. ® Intel ICH7 Family Datasheet Table 5-21 shows which bits are set to their default state when S5) when the – ...
Page 148
... PMBase + 2Ch Register (GPE0_EN) General Purpose Event 0 Enables PMBase + 2Ch Register (GPE0_EN) General Purpose Event 0 Enables PMBase + 2Ch Register (GPE0_EN) Functional Description Default Bit(s) State 7 12: ® Intel ICH7 Family Datasheet ...
Page 149
... Standard Outputs to processor: A20M#, SMI#, NMI, INIT#, INTR, STPCLK#, IGNNE#, CPUSLP# (supported only on desktop platforms), CPUPWRGD • Standard Input from processor: FERR# • Intel SpeedStep Mobile configurations) Most ICH7 outputs to the processor use standard buffers. The ICH7 has separate V_CPU_IO signals that are pulled up at the system level to the processor voltage, and thus determines VOH for the outputs to the processor ...
Page 150
... IRQ13 and drives IGNNE# active. IGNNE# remains active until FERR# is driven inactive. IGNNE# is not driven active unless FERR# is active. 150 Functional Description Comment transition on RCIN# must occur ® before the Intel ICH7 will arm INIT generated again. NOTE: RCIN# signal is expected to be high during S3 and low during HOT S3 , S4, and S5 states ...
Page 151
... STP_CPU# signal to effectively stop the processor’s clock (internally) in the states in which STP_CPU# can be used to stop the processor’s clock externally. ® Intel ICH7 Family Datasheet Comment Can instead be routed to generate an SCI, through the NMI2SCI_EN bit (Device 31:Function 0, TCO Base + 08h, bit 11) ...
Page 152
... Upon exit from those states, the processors will have their power restored. 152 Difference Generally not used, but still supported by Intel Used for S1 State as well as preparation for entry to S3–S5 Also allows for THERM# based throttling (not via ACPI control methods). Should be connected to both processors. ...
Page 153
... ICH7 and System Power States Table 5-25 shows the power states defined for ICH7-based platforms. The state names generally match the corresponding ACPI states. Table 5-25. General Power States for Systems Using Intel State/ Substates Full On: Processor operating. Individual devices may be shut down to save power ...
Page 154
... Table 5-25. General Power States for Systems Using Intel State/ Substates Stop-Clock: The STPCLK# signal goes active to the processor. The processor performs a Stop-Grant cycle, halts its instruction stream. ICH7 then asserts G0/S0/C3 DPSLP# followed by STP_CPU#, which forces the clock generator to stop the (Mobile/Ultra processor clock ...
Page 155
... Functional Description Table 5-26. State Transition Rules for Intel Present State • Processor halt instruction • Level 2 Read • Level 3 Read (Mobile Only) G0/S0/C0 • Level 4 Read (Mobile Only) • SLP_EN bit set • Power Button Override • Mechanical Off/Power Failure • Any Enabled Break Event • ...
Page 156
... HOT HOT ® including the Intel ICH7 core well, powered to reduce the cost of external power plane logic. SLP_S3# is only used to remove power to the processor and to shut system clocks. This impacts the board design, but there is no specific ICH7 bit or strap needed to indicate which option is selected ...
Page 157
... TCO SMI — Year 2000 Rollover TCO SMI — TCO TIMEROUT TCO SMI — OS writes to TCO_DAT_IN register TCO SMI — Message from (G)MCH ® Intel ICH7 Family Datasheet Section 10.1.14). The interrupt remains asserted until all SCI SCI SMI Additional Enables Yes ...
Page 158
... BIOS_RLS written to GBL_RLS written to Write to B2h register Periodic timer expires 64 ms timer expires Enhanced USB Legacy Support Event Enhanced USB Intel Specific Event UHCI USB Legacy logic Serial IRQ SMI reported Device monitors match address in its range SMBus Host Controller SMBus Slave SMI message ...
Page 159
... Break event. Based on the break event, the ICH7 returns the system to C0 state. (Mobile/Ultra Mobile Only) C4. The break events from C1 are indicated in the processor’s datasheet. ® Intel ICH7 Family Datasheet Table 5-29 lists the possible break events from C2, C3, or 159 ...
Page 160
... NOT be treated as a break event. Instead, there will be a return only to the C2 state. Only available if FERR# enabled for break event C2, C3, C4 indication (See FERR# Mux Enable in GCS, Chipset Config Registers:Offset 3410h:bit 6) Intel Functional Description ® ICH7 Family Datasheet ...
Page 161
... CLKRUN#: Used by PCI and LPC peripherals to request the system PCI clock to run • STP_PCI#: Used to stop the system PCI clock Note: The 33 MHz clock to the ICH7 is “free-running” and is not affected by the STP_PCI# signal. ® Intel ICH7 Family Datasheet 161 ...
Page 162
... PCI clock edge occurs at the LPC device after the assertion of STP_PCI#. Upon deassertion of STP_PCI#, the ICH7 assumes that the LPC device receives its first clock rising edge corresponding to the ICH7’s second PCI clock rising edge after the deassertion. 162 Functional Description ® Intel ICH7 Family Datasheet ...
Page 163
... Wake events that occur while BATLOW# is asserted are latched by the ICH7, and the system wakes after BATLOW# is de-asserted. ® Intel ICH7 Family Datasheet Comment ICH7 asserts the STPCLK# signal. It also has the option to assert CPUSLP# Table 5-31 ...
Page 164
... Table 5-31. Causes of Wake Events Cause RTC Alarm Power Button GPI[0:15] Classic USB LAN (Desktop and Mobile only) RI# ® AC ‘97 / Intel High Definition Audio Primary PME# Secondary PME# PCI_EXP_WAKE# (Desktop and Mobile only) PCI_EXP PME Message (Desktop and Mobile only) SMBALERT# SMBus Slave ...
Page 165
... PWROK_FLR bit is set. If RSMRST# goes low, PWR_FLR is set. Note: Although PME_EN is in the RTC well, this signal cannot wake the system after a power loss. PME_EN is cleared by RTCRST#, and PME_STS is cleared by RSMRST#. ® Intel ICH7 Family Datasheet summarizes the use of GPIs as wake events. Power Well Wake From ...
Page 166
... Furthermore, the ICH7 waits for the STOP- GRANT cycle before starting the count of the time the STPCLK# signal is active. 166 AFTERG3_EN bit Transition When Power Returns Functional Description ® Intel ICH7 Family Datasheet ...
Page 167
... State S0/Cx PWRBTN# goes low S1–S5 PWRBTN# goes low G3 PWRBTN# pressed PWRBTN# held low S0–S4 for at least 4 consecutive seconds ® Intel ICH7 Family Datasheet Event Transition/Action SMI# or SCI generated (depending on SCI_EN) Wake Event. Transitions to S0 state None Unconditional transition to S5 state Table 5-34 ...
Page 168
... Break event. Table 5-35. Transitions Due to RI# Signal Present State S0 RI# Active S1–S5 RI# Active Note: Filtering/Debounce on RI# will not be done in ICH7. It can be in modem or external. 168 Event RI_EN X Ignored 0 Ignored 1 Wake Event Functional Description Event ® Intel ICH7 Family Datasheet ...
Page 169
... THRMTRIP# is now inactive. This is the equivalent of “latching” the thermal trip event state reached step #1, otherwise stay here. If the ICH7 does not reach S5, the ICH7 does not reboot until power is cycled. ® Intel ICH7 Family Datasheet 169 ...
Page 170
... For some other loss (e.g., Microsoft MS-DOS*) the BIOS should restore the timer back to 54.6 ms before passing control to the operating system. If the BIOS is entering ALT access mode before entering the suspend state it is not necessary to restore the timer contents after the exit from ALT access mode. 170 Functional Description ® Intel ICH7 Family Datasheet ...
Page 171
... DMA Chan 3 base address high 2 byte DMA Chan 3 base count low 1 byte 07h 2 DMA Chan 3 base count high 2 byte ® Intel ICH7 Family Datasheet Table 5-36 have read paths in ALT access mode. The access I Data Access Addr Rds 40h 7 41h 1 42h ...
Page 172
... DMA Chan 7 base count high 2 byte 1 1 DMA Chan 4–7 Command 2 DMA Chan 4–7 Request DMA Chan 4 Mode: Bits(1: DMA Chan 5 Mode: Bits(1: DMA Chan 6 Mode: Bits(1: DMA Chan 7 Mode: Bits(1: 11. ® Intel ICH7 Family Datasheet ...
Page 173
... The SLP_S3# output signal can be used to cut power to the system core supply, since it only goes active for the STR state (typically mapped to ACPI S3). Power must be maintained to the ICH7 resume well, and to any other circuits that need to generate Wake signals from the STR state. ® Intel ICH7 Family Datasheet Table 5-37. Value Returned ...
Page 174
... PWROK and RSMRST# are sampled using the RTC clock. Therefore, low times that are less than one RTC clock period may not be detected by the ICH7 the case of true PWROK failure, PWROK goes low first before the VRMPWRGD. 174 Functional Description ® Intel ICH7 Family Datasheet ...
Page 175
... Buses should be halted (and held known state to avoid a floating input (perhaps to some other device). Floating inputs can cause extra power consumption. Based on the above principles, the following measures are taken: • During S3 (STR), all signals attached to powered down planes are tri-stated or driven low. ® Intel ICH7 Family Datasheet 175 ...
Page 176
... Used by ACPI timers. Stopped based on MHz Generator SLP_S3# assertion. AC-link. Control policy is determined by the clock source. AC ’97 MHz Codec NOTE: Becomes clock output when Intel High Definition Audio is enabled. 0.8 to LAN LAN Connect Interface. Control policy is determined by Connect the clock source. ® ICH7 to Clock and on the way ...
Page 177
... When software (not the SMI# handler) attempts to access the device, a trap occurs (the cycle does not really go to the device and an SMI# is generated). 3. The SMI# handler turns on the device and turns off the trap The SMI# handler exits with an I/O restart. This allows the original software to continue. ® Intel ICH7 Family Datasheet 177 ...
Page 178
... The software can also directly read the status of the INTRUDER# signal (high or low) by clearing and then reading the INTRD_DET bit. This allows the signal to be used as a GPI if the intruder function is not required. 178 Functional Description Section 7.1.56) ® Intel ICH7 Family Datasheet ...
Page 179
... The event messages are sent based on events occurring. The heartbeat messages are sent every seconds. When an event occurs, the ICH7 sends a new message and increments the SEQ[3:0] field. For heartbeat messages, the sequence number does not increment. ® Intel ICH7 Family Datasheet Section 5.15.2). 179 ...
Page 180
... SMBus reset messages) occur after a third timeout of the watchdog timer. If the intervention occurs before the third timeout, then jump to rule/step 11. 4. After step 3 (third timeout), if the user does a Power Button Override, the system goes state. The ICH7 continues sending heartbeats at this point. 180 Functional Description ® Intel ICH7 Family Datasheet ...
Page 181
... If the system (S1–S4) state, the ICH7 sends a heartbeat message every 30– 32 seconds event occurs prior to the system being shutdown, the ICH7 immediately sends an event message with the next incremented sequence number. After the event message, the ICH7 resumes sending heartbeat messages. ® Intel ICH7 Family Datasheet 181 ...
Page 182
... Comment 1 = This bit is set if the intruder detect bit is set (INTRD_DET). ® This bit is set if the Intel ICH7 THERM# input signal is asserted This bit is set if the processor failed to fetch its first instruction This bit is set when software writes the SEND_NOW bit. ...
Page 183
... Control and Timing registers. When a drive is enabled for synchronous DMA mode operation, the DMA transfers are executed with the synchronous DMA timings. The PIO transfers are executed using compatible timings or fast timings if also enabled. ® Intel ICH7 Family Datasheet Comment This is a sequence number. It initially is 0, and increments each time the ICH7 sends a new message ...
Page 184
... This ensures that the chip selects are deasserted for at least two PCI clocks between the two cycles. 184 Table IORDY Startup Recovery Time Sample Latency (RCT) Point (ISP 2–5 1–4 Intel Functional Description 5-41. Shutdown Latency ® ICH7 Family Datasheet ...
Page 185
... If greater than the disk transfer request, the driver must terminate the bus master transaction (by setting bit 0 in the Bus Master IDE Command Register to 0) when the drive issues an interrupt to signal transfer completion. ® Intel ICH7 Family Datasheet 185 ...
Page 186
... IDE interrupts cannot be communicated through PCI devices or the serial IRQ stream. Note: The combined mode is not supported on ICH7-U Ultra Mobile. ICH7-U does not contain a SATA controller. 186 Byte 2 Byte 1 Byte 0 Byte Count [15:1] Functional Description Main Memory Memory Region o o ® Intel ICH7 Family Datasheet ...
Page 187
... Active bit reset or the Interrupt bit set, can be assured that all data destined for system memory has been transferred and that data is valid in system memory. Table 5-42 describes how to interpret the Interrupt and Active bits in the Status Register after a DMA transfer has started. ® Intel ICH7 Family Datasheet 187 ...
Page 188
... Specifics of the error have to be determined using bus-specific information. If the Error bit is not set, then the PRD's specified a smaller size than the IDE transfer size. Functional Description ® Intel ICH7 Family Datasheet ...
Page 189
... IDE channel Programmed I/O (PIO) cycle is executed to the IDE channel currently running the burst, or upon transferring the last data from the final PRD. ® Intel ICH7 Family Datasheet reads) providing data and toggling STROBE. Data is transferred – ...
Page 190
... Bus-Master IDE registers occurs while trapping is enabled for the device being accessed, then the register is updated, an SMI# is generated, and the device activity status bits (Device 31:Function 1:Offset C4h) are updated indicating that a trap occurred. 190 Functional Description Section 15.1.26) contain control for generating ® Intel ICH7 Family Datasheet – ...
Page 191
... SATA interface transfer rates are independent of UDMA mode settings. SATA interface transfer rates will operate at the bus’s maximum speed, regardless of the UDMA mode reported by the SATA device or the system BIOS. Table 5-43. SATA Features Support in Intel Feature Native Command Queing (NCQ) ...
Page 192
... A mechanism for one active host connection to communicate with multiple devices Technology that allows for an outside the box connection meters (when using the cable defined in SATA-IO) Intel Functional Description ® ICH7 Family Datasheet ...
Page 193
... RAID 5 is well suited for applications that require high amounts of storage while maintaining fault tolerance. By using the ICH7’s built-in Intel Matrix Storage Technology, there is no loss of PCI resources (request/grant pair) or add-in card slot. Intel Matrix Storage Technology is not available in all ICH7 components. ICH7-M DH supports RAID Level 0, 1 ...
Page 194
... Intel Matrix Storage Manager RAID Option ROM The Intel Matrix Storage Manager RAID Option ROM is a standard PnP Option ROM that is easily integrated into any System BIOS. When in place, it provides the following three primary functions: • Provides a text mode user interface that allows the user to manage the RAID configuration on the system in a pre-operating system environment. Its feature set is kept simple to keep size to a minimum, but allows the user to create & ...
Page 195
... The interface will be treated device is present on the cable, and power will be minimized. When returning from a D3 state, an internal reset will not be performed. ® Intel ICH7 Family Datasheet Power ® Intel ICH SATA Controller = D0 Device = D0 Device = D1 PHY = PHY = PHY = PHY = ...
Page 196
... SATALED active-low open-collector output. When SATALED# is low, the LED should be active. When SATALED# is high, the LED should be inactive. 5.17.6 AHCI Operation (Intel The ICH7 provides hardware support for Advanced Host Controller Interface (AHCI), a programming interface for SATA host controllers developed thru a joint industry effort (AHCI not available on all ICH7 components ...
Page 197
... Each tick is less than or equal to 100 ns, so this represents an error of less than 0.2%. 3. The timer is monotonic. It does not return the same value on two consecutive reads (unless the counter has rolled over and reached the same value). ® Intel ICH7 Family Datasheet 197 ...
Page 198
... Software sets the ENABLE_CNF bit to enable interrupts. 198 Table 5-45. APIC Mapping IRQ0 IRQ2 IRQ8 IRQ8 Per IRQ Routing Field Section 20.1.5). Functional Description Comment In this case, the 8254 timer will not cause any interrupts In this case, the RTC will not cause any interrupts. ® Intel ICH7 Family Datasheet ...
Page 199
... If Timer 0 is set up to generate a periodic interrupt, the software can check to see how much time remains until the next interrupt by checking the timer value register. ® Intel ICH7 Family Datasheet Section 5.10 for 199 ...
Page 200
... Full details on this implementation are given in the Universal Serial Bus Specification, Revision 2.0. 5.19.4 Bus Protocol 5.19.4.1 Bit Ordering Bits are sent out onto the bus least significant bit (LSb) first, followed by next LSb, through to the most significant bit (MSb) last. 200 Functional Description ® Intel ICH7 Family Datasheet ...