AT45DB081B-CNU SL383 Atmel, AT45DB081B-CNU SL383 Datasheet - Page 14
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AT45DB081B-CNU SL383
Manufacturer Part Number
AT45DB081B-CNU SL383
Description
Manufacturer
Atmel
Datasheet
1.AT45DB081B-CNU_SL383.pdf
(33 pages)
- Current page: 14 of 33
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Input Test Waveforms and Measurement Levels
Output Test Load
AC Waveforms
Waveform 1 – Inactive Clock Polarity Low and SPI Mode 0
Waveform 2 – Inactive Clock Polarity High and SPI Mode 3
14
AT45DB081B
SCK
SCK
SO
SO
CS
CS
SI
SI
t
Two different timing diagrams are shown below. Waveform 1 shows the SCK signal being low
when CS makes a high-to-low transition, and Waveform 2 shows the SCK signal being high
when CS makes a high-to-low transition. Both waveforms show valid timing diagrams. The setup
and hold times for the SI signal are referenced to the low-to-high transition on the SCK signal.
Waveform 1 shows timing that is also compatible with SPI Mode 0, and Waveform 2 shows tim-
ing that is compatible with SPI Mode 3.
R
, t
HIGH IMPEDANCE
HIGH Z
F
< 3 ns (10% to 90%)
t
CSS
t
t
SU
t
V
CSS
t
DRIVING
SU
LEVELS
AC
t
VALID IN
WL
VALID IN
0.45V
VALID OUT
2.4V
t
WH
t
WH
t
t
V
HO
DEVICE
UNDER
TEST
t
H
t
H
t
WL
VALID OUT
2.0
0.8
30 pF
t
HO
AC
MEASUREMENT
LEVEL
t
CSH
t
CSH
HIGH IMPEDANCE
HIGH IMPEDANCE
t
t
t
t
DIS
DIS
CS
CS
2225J–DFLSH–2/08
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