24LC128-I/SMG Microchip, 24LC128-I/SMG Datasheet - Page 5

• Manufacturer Part Number: 24LC128-I/SMG
• Description: ind, Semiconductors and Actives, EEPROMs, ser, Memory
• Manufacturer: Microchip

2.0
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
2.1
The A0, A1 and A2 inputs are used by the 24XX128 for
multiple device operations. The levels on these inputs
are compared with the corresponding bits in the slave
address. The chip is selected if the compare is true.
For the MSOP package only, pins A0 and A1 are not
connected.
Up to eight devices (two for the MSOP package) may
be connected to the same bus by using different Chip
Select bit combinations. These inputs must be
In most applications, the chip address inputs A0, A1
and A2 are hard-wired to logic ‘0’ or logic ‘1’. For
applications in which these pins are controlled by a
microcontroller or other programmable device, the chip
address pins must be driven to logic ‘0’ or logic ‘1’
before normal device operation can proceed.
2.2
This is a bidirectional pin used to transfer addresses
and data into and out of the device. It is an open drain
terminal. Therefore, the SDA bus requires a pull-up
resistor to V
400 kHz and 1 MHz).
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
© 2005 Microchip Technology Inc.
connected to either V
A0
A1
(NC)
A2
V
SDA
SCL
(NC)
WP
V
SS
CC
Name
PIN DESCRIPTIONS
A0, A1, A2 Chip Address Inputs
Serial Data (SDA)
CC
(typical 10 k
PIN FUNCTION TABLE
8-pin
PDIP
—
—
1
2
3
4
5
6
7
8
CC
or V
SS
8-pin
SOIC
.
for 100 kHz, 2 k
—
—
1
2
3
4
5
6
7
8
TSSOP
8-pin
24AA128/24LC128/24FC128
—
—
1
2
3
4
5
6
7
8
for
MSOP
8-pin
1, 2
—
—
—
3
4
5
6
7
8
2.3
This input is used to synchronize the data transfer to
and from the device.
2.4
This pin must be connected to either V
to V
write operations are inhibited but read operations are
not affected.
3.0
The 24XX128 supports a bidirectional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter and a device
receiving data as a receiver. The bus must be
controlled by a master device which generates the
Serial Clock (SCL), controls the bus access and
generates the Start and Stop conditions while the
24XX128 works as a slave. Both master and slave can
operate as a transmitter or receiver, but the master
device determines which mode is activated.
SS
8-pin
DFN
, write operations are enabled. If tied to V
—
—
1
2
3
4
5
6
7
8
Serial Clock (SCL)
Write-Protect (WP)
FUNCTIONAL DESCRIPTION
User Configurable Chip Select
User Configurable Chip Select
Not Connected
User Configurable Chip Select
Ground
Serial Data
Serial Clock
Not Connected
Write-Protect Input
+1.8V to 5.5V (24AA128)
+2.5V to 5.5V (24LC128)
+1.8V to 5.5V (24FC128)
Function
DS21191N-page 5
SS
or V
CC
. If tied
CC
,