MAX3362EKATG16 Maxim Integrated Products, Inc., MAX3362EKATG16 Datasheet - Page 10

• Manufacturer Part Number: MAX3362EKATG16
• Description: Max3362 3.3v, High-speed, Rs-485/rs-422 Transceiver In Sot Package
• Manufacturer: Maxim Integrated Products, Inc.

3.3V, High-Speed, RS-485/RS-422 Transceiver in
SOT Package
Table 1. Transmitter Functional Table
The MAX3362 has a 1/8-unit-load receiver input imped-
ance, allowing up to 256 transceivers to be connected
simultaneously on a bus. The MAX3362 is designed for
half-duplex communication.
The driver transfers single-ended input (DI) to differen-
tial outputs (A, B). The driver enable (DE) input controls
the driver. When DE is high, driver outputs are enabled.
These outputs are high impedance when DE is low.
When the driver is enabled, setting DI low forces the
noninverting output (A) low and inverting output (B)
high. Conversely, drive DI high to force noninverting
output high and inverting output low (Table 1).
Drive RE high and DE low (disable both receiver and
driver outputs) to enter low-power shutdown mode.
The receiver reads differential inputs from the bus lines
(A, B) and transfers this data as a single-ended output
(RO). The receiver enable (RE) input controls the
receiver. Drive RE low to enable the receiver. Driving
RE high places RO into a high-impedance state.
When the receiver is enabled, RO is high if (A-B) ≥
200mV. RO is low if (A-B) ≤ -200mV.
10
Table 2. Receiver Functional Table
RE
______________________________________________________________________________________
X
X
0
1
RE
0
0
1
1
INPUTS
DE
1
1
0
0
INPUTS
DE
TRANSMITTING
X
X
1
0
RECEIVING
DI
1
0
X
X
≤ -200mV
≥ 200mV
A – B
High Z
X
X
A
1
0
OUTPUTS
Shutdown
Receiver
Shutdown
OUTPUT
High-Z
High Z
RO
Driver
1
0
B
0
1
Drive RE high and DE low (disable both receiver and
driver outputs) to enter low-power shutdown mode.
When circuit boards are inserted into a hot or powered
backplane, disturbances to the enable and differential
receiver inputs can lead to data errors. Upon initial cir-
cuit board insertion, the processor undergoes its
power-up sequence. During this period, the output dri-
vers are high impedance and are unable to drive the
DE input of the MAX3362 to a defined logic level.
Leakage currents up to 10µA from the high-impedance
output could cause DE to drift to an incorrect logic
state. Additionally, parasitic circuit board capacitance
could cause coupling of V
tors could improperly enable the driver.
When V
low for at least 10µs and until the current into DE
exceeds 200µA. After the initial power-up sequence,
the pulldown circuit becomes transparent, resetting the
hot-swap tolerable input.
The MAX3362 enable inputs feature hot-swap capability.
At the input there are two NMOS devices, M1 and M2
(Figure 8). When V
timer turns on M2 and sets the SR latch, which also turns
on M1. Transistors M2, a 300µA current sink, and M1, a
30µA current sink, pull DE to GND through an 8kΩ resis-
tor. M2 is designed to pull DE to the disabled state
against an external parasitic capacitance up to 100pF
that may drive DE high. After 10µs, the timer deactivates
M2 while M1 remains on, holding DE low against three-
state leakages that may drive DE high. M1 remains on
until an external source overcomes the required input
current. At this time, the SR latch resets and M1 turns off.
When M1 turns off, DE reverts to a standard, high-
impedance CMOS input. Whenever V
1V, the hot-swap input is reset.
For RE there is a complimentary circuit employing two
PMOS devices pulling RE to V
The circuit of Figure 9 shows a typical offset termination
used to guarantee a greater than 200mV offset when a
line is not driven (the 50pF represents the minimum
parasitic capacitance that would exist in a typical appli-
cation). During a hot-swap event when the driver is
CC
rises, an internal pulldown circuit holds DE
CC
ramps from 0, an internal 10µs
CC
Hot-Swap Input Circuitry
Hot-Swap Line Transient
Hot-Swap Capability
or GND to DE. These fac-
CC
.
Hot-Swap Input
CC
drops below