AD9653BCPZ-125 Analog Devices, AD9653BCPZ-125 Datasheet - Page 9

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AD9653BCPZ-125

Manufacturer Part Number
AD9653BCPZ-125
Description
the ad9653 is a quad, 16-bit, 125 msps analog-to-digital converter (adc) with an...
Manufacturer
Analog Devices
Datasheet

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
AD9653BCPZ-125
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Data Sheet
TIMING SPECIFICATIONS
Table 7.
Parameter
SYNC TIMING REQUIREMENTS
SPI TIMING REQUIREMENTS
Timing Diagrams
Refer to the Memory Map Register Descriptions section and Table 23 for SPI register settings.
BYTEWISE
BITWISE
t
t
t
t
t
t
t
t
t
t
t
SSYNC
HSYNC
DS
DH
CLK
S
H
HIGH
LOW
EN_SDIO
DIS_SDIO
MODE
MODE
DDR
SDR
FCO–
VIN±x
DCO–
DCO+
CLK+
FCO–
FCO+
FCO+
CLK–
D0–A
D0+A
D1–A
D1+A
D0–A
D0+A
D1–A
D1+A
DCO
N – 1
t
A
Description
SYNC to rising edge of CLK+ setup time
SYNC to rising edge of CLK+ hold time
See Figure 75
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the SCLK
Setup time between CSB and SCLK
Hold time between CSB and SCLK
SCLK pulse width high
SCLK pulse width low
Time required for the SDIO pin to switch from an input to an output relative to the
SCLK falling edge (not shown in Figure 75)
Time required for the SDIO pin to switch from an output to an input relative to the
SCLK rising edge (not shown in Figure 75)
t
EH
t
t
FCO
t
PD
CPD
Figure 2. 16-Bit DDR/SDR, Two-Lane, 1× Frame Mode (Default)
N – 17
N – 17
N – 17
N – 17
MSB
MSB
D14
D07
t
N – 17
N – 17
N – 17
N – 17
t
FRAME
D06
D14
EL
D12
D13
N – 17
N – 17
Rev. 0 | Page 9 of 40
N – 17
N – 17
D10
D11
D05
D13
N – 17
N – 17
N – 17
N – 17
D04
D12
D08
D09
N
t
N – 17
N – 17
N – 17
N – 17
DATA
D06
D07
D03
D11
N – 17
N – 17
N – 17
N – 17
D02
D10
D04
D05
N – 17
N – 17
N – 17
N – 17
D01
D09
D02
D03
N – 17
N – 17
N – 17
N – 17
LSB
LSB
D08
D01
t
LD
N – 16
N – 16
N – 16
N – 16
MSB
MSB
D14
D07
N – 16
N – 16
N – 16
N – 16
D12
D13
D06
D14
N – 16
N – 16
N – 16
N – 16
D10
D11
D05
D13
N – 16
N – 16
N – 16
N – 16
D08
D09
D04
D12
N + 1
N – 16
N – 16
N – 16
N – 16
D06
D07
D03
D11
N – 16
N – 16
N – 16
N – 16
Limit
0.24
0.40
2
2
40
2
2
10
10
10
10
D02
D10
D04
D05
N – 16
N – 16
N – 16
N – 16
AD9653
D02
D03
D01
D09
Unit
ns typ
ns typ
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
N – 16
N – 16
N – 16
N – 16
LSB
LSB
D08
D01

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