A54SX08A-PQG208I Microsemi, A54SX08A-PQG208I Datasheet - Page 39

• Manufacturer Part Number: A54SX08A-PQG208I
• Description: Ic Fpga Sx 12k Gates 208-Pqfp
• Manufacturer: Microsemi

Table 2-14 • A54SX08A Timing Characteristics (Continued)
Parameter
t
t
t
t
Input Module Predicted Routing Delays
t
t
t
t
t
t
Notes:
1. For dual-module macros, use t
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
INYH
INYL
INYH
INYL
IRD1
IRD2
IRD3
IRD4
IRD8
IRD12
performance. Post-route timing analysis or simulation is required to determine actual performance.
(Worst-Case Commercial Conditions, V
Input Data Pad to Y High 5 V PCI
Input Data Pad to Y Low 5 V PCI
Input Data Pad to Y High 5 V TTL
Input Data Pad to Y Low 5 V TTL
FO = 1 Routing Delay
FO = 2 Routing Delay
FO = 3 Routing Delay
FO = 4 Routing Delay
FO = 8 Routing Delay
FO = 12 Routing Delay
Description
PD
+ t
RD1
+ t
PDn
2
, t
RCO
CCA
+ t
RD1
= 2.25 V
+ t
Min. Max. Min. Max. Min.
v5.3
PDn
–2 Speed
,
V
, or t
CCI
0.5
0.8
0.5
0.8
0.3
0.5
0.6
0.8
1.4
= 3.0 V, T
2
PD1
+ t
RD1
–1 Speed
J
+ t
= 70°C)
SUD
0.6
0.9
0.6
0.9
0.3
0.5
0.7
0.9
1.5
2.2
, whichever is appropriate.
Std. Speed
Max. Min. Max.
0.7
1.1
0.7
1.1
0.4
0.6
0.8
1.8
2.6
1
–F Speed
SX-A Family FPGAs
0.9
1.5
0.9
1.5
0.6
0.8
1.1
1.4
2.5
3.6
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2-19