9248AG-195LF Integrated Device Technology, 9248AG-195LF Datasheet - Page 14

• Manufacturer Part Number: 9248AG-195LF
• Manufacturer: Integrated Device Technology

0375E—12/15/08
ICS9248-195
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
3. All other clocks continue to run undisturbed.
4. CLK_STOP# is shown in a high (true) state.
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9248-195. It is used to turn off the PCICLK clocks for low power
operation. PCI_STOP# is synchronized by the ICS9248-195 internally. The minimum that the PCICLK clocks are
enabled (PCI_STOP# high pulse) is at least 10 PCICLK clocks. PCICLK clocks are stopped in a low state and started
with a full high pulse width guaranteed. PCICLK clock on latency cycles are only three rising PCICLK clocks, off latency
is one PCICLK clock.
inside the ICS9248.
(Free-running)
CLK_STOP#
PCI_STOP#
PCICLK_F
PCICLK_F
CPUCLK
(Internal)
(Internal)
PCICLK
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