EP2S15 ALTERA [Altera Corporation], EP2S15 Datasheet - Page 162
EP2S15
Manufacturer Part Number
EP2S15
Description
Stratix II Device Family
Manufacturer
ALTERA [Altera Corporation]
Datasheet
1.EP2S15.pdf
(238 pages)
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Timing Model
5–26
Stratix II Device Handbook, Volume 1
LVTTL
LVCMOS
2.5 V
1.8 V
1.5 V
PCI
PCI-X
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.8-V HSTL Class I
Table 5–35. Timing Measurement Methodology for Input Pins (Part 1 of 2)
(6)
(5)
(5)
(5)
(6)
(5)
(5)
I/O Standard
Figure 5–6. Measurement Setup for t
Table 5–35
Din
Din
OE
OE
specifies the input timing measurement setup.
V
CCIO
3.135
3.135
2.375
1.710
1.425
2.970
2.970
2.325
2.325
1.660
1.660
1.660
(V)
Measurement Conditions
t
t
1 MΩ
1 MΩ
ZX
ZX
V
, Tristate to Driving High
Dout
, Tristate to Driving Low
Dout
1.163
1.163
0.830
0.830
0.830
REF
(V)
zx
Dout
Dout
Din
Din
OE
OE
Edge Rate (ns)
Disable
Disable
3.135
3.135
2.375
1.710
1.425
2.970
2.970
2.325
2.325
1.660
1.660
1.660
Notes (1)–(4)
Enable
Enable
½ V
½ V
CCINT
CCINT
Measurement Point
t
t
zh
zl
Altera Corporation
V
M E A S
1.5675
1.5675
1.1875
0.7125
1.1625
1.1625
0.855
1.485
1.485
0.83
0.83
0.83
May 2007
(V)
½ V
½ V
“1”
“0”
CCIO
CCIO