EX256-CS100A ACTEL [Actel Corporation], EX256-CS100A Datasheet - Page 30

• Manufacturer Part Number: EX256-CS100A
• Description: eX Family FPGAs
• Manufacturer: ACTEL [Actel Corporation]

Pin Description
CLKA/B
These pins are clock inputs for clock distribution
networks. Input levels are compatible with standard TTL
or LVTTL specifications. The clock input is buffered prior
to clocking the R-cells. If not used, this pin must be set
LOW or HIGH on the board. It must not be left floating.
GND
LOW supply voltage.
HCLK
This pin is the clock input for sequential modules. Input
levels are compatible with standard TTL or LVTTL
specifications. This input is directly wired to each R-cell
and offers clock speeds independent of the number of R-
cells being driven. If not used, this pin must be set LOW
or HIGH on the board. It must not be left floating.
I/O
The I/O pin functions as an input, output, tristate, or
bidirectional buffer. Based on certain configurations,
input and output levels are compatible with standard
TTL or LVTTL specifications. Unused I/O pins are
automatically tristated by the Designer software.
LP
Controls the low power mode of the eX devices. The
device is placed in the low power mode by connecting
the LP pin to logic HIGH. In low power mode, all I/Os are
tristated, all input buffers are turned OFF, and the core
of the device is turned OFF. To exit the low power mode,
the LP pin must be set LOW. The device enters the low
power mode 800 ns after the LP pin is driven to a logic
HIGH. It will resume normal operation 200 µs after the LP
pin is driven to a logic LOW. LP pin should not be left
floating. Under normal operating condition it should be
tied to GND via 10 kΩ resistor.
NC
This pin is not connected to circuitry within the device.
These pins can be driven to any voltage or can be left
floating with no effect on the operation of the device.
PRA/PRB, I/O
The Probe pin is used to output data from any user-
defined design node within the device. This diagnostic
pin can be used independently or in conjunction with the
other probe pin to allow real-time diagnostic output of
any signal path within the device. The Probe pin can be
used as a user-defined I/O when verification has been
completed.
permanently disabled to protect programmed design
confidentiality.
1 -2 6
eX Family FPGAs
The
Routed Clock A and B
Ground
Dedicated (Hardwired)
Array Clock
Input/Output
Low Power Pin
No Connection
Probe A/B
pin’s
probe
capabilities
can
be
v4.3
TCK, I/O
Test clock input for diagnostic probe and device
programming. In flexible mode, TCK becomes active
when the TMS pin is set LOW (refer to
page
boundary scan state machine reaches the “logic reset”
state.
TDI, I/O
Serial input for boundary scan testing and diagnostic
probe. In flexible mode, TDI is active when the TMS pin is
set LOW (refer to
functions as an I/O when the boundary scan state
machine reaches the “logic reset” state.
TDO, I/O
Serial output for boundary scan testing. In flexible mode,
TDO is active when the TMS pin is set LOW (refer to
Table 1-4 on page
the boundary scan state machine reaches the "logic
reset" state. When Silicon Explorer is being used, TDO
will act as an output when the "checksum" command is
run. It will return to user I/O when "checksum" is
complete.
TMS
The TMS pin controls the use of the IEEE 1149.1
Boundary scan pins (TCK, TDI, TDO, TRST). In flexible
mode when the TMS pin is set LOW, the TCK, TDI, and
TDO pins are boundary scan pins (refer to
page
they will remain in that mode until the internal
boundary scan state machine reaches the “logic reset”
state. At this point, the boundary scan pins will be
released and will function as regular I/O pins. The “logic
reset” state is reached five TCK cycles after the TMS pin is
set HIGH. In dedicated test mode, TMS functions as
specified in the IEEE 1149.1 specifications.
TRST, I/O
Once it is configured as the JTAG Reset pin, the TRST pin
functions as an active-low input to asynchronously
initialize or reset the boundary scan circuit. The TRST pin
is equipped with an internal pull-up resistor. This pin
functions as an I/O when the “Reserve JTAG Reset Pin” is
not selected in the Designer software.
V
Supply voltage for I/Os.
V
Supply voltage for Array.
CCI
CCA
1-9). This pin functions as an I/O when the
1-9). Once the boundary scan pins are in test mode,
Test Clock
Test Data Input
Test Data Output
Test Mode Select
Boundary Scan Reset Pin
Supply Voltage
Supply Voltage
1-9). This pin functions as an I/O when
Table 1-4 on page
1-9). This pin
Table 1-4 on
Table 1-4 on