EM65571AGH EMC [ELAN Microelectronics Corp], EM65571AGH Datasheet - Page 98

• Manufacturer Part Number: EM65571AGH
• Description: 130COM / 128SEG 65K Color STN LCD Driver
• Manufacturer: EMC [ELAN Microelectronics Corp]

EM65571
130COM/128SEG 65K Color STN LCD Driver
92 •
8.2.21 Internal Register Read Address
Note: During a reset: {RA3, RA2, RA1, RA0} = BH
The RA register is set to specify the address for the register read operation. The EM65571
has many registers, including a register bank. There are 4 steps necessary to read a
specific register.
8.2.22 Internal Register Data Read
Note: The asterisk “*” mark means “Don’t care”
This command is used to read data from an internal register. Before executing the
command, you need to set the address and RE flag to read data from the internal register.
8.2.23 Windows End X Address
Note: During a reset: {EX3, EX2, EX1, EX0} = 0H, read address: 0H
Note: During a reset: {EX7, EX6, EX5, EX4} = 0H, read address: 1H)
Set the EX registers to the X-direction end address for Windows function.
D7 D6 D5 D4
D7
D7
D7
*
1
0
0
1. Write 04H to the RE register to access the RA register.
2. Write a specific register address to the RA register.
3. Write a specific register bank to the RE register.
4. Read the specific contents.
BF1
*
The asterisk “*” mark means “Don’t care”
0
0
1
1
D6
D6
D6
1
0
0
BF
BF1~BF0: Select the booster operating frequency. When the boosting frequency
is high, the driving ability of the booster becomes high, but the current
consumption is increased. When adjusting the boosting frequency, consider the
external capacitors and the current consumption.
*
D5
D5
D5
0
0
0
*
Internal Register Read Data
D4
D4
D4
1
1
0
BF0
D3
0
1
0
1
RA3 RA2 RA1 RA0
EX7 EX6 EX5 EX4
EX3 EX2 EX1 EX0
D3
D3
D3
D2
D2
D2
D2
D1
D1
D1
D1
Booster Operating Clock Frequency
D0
D0
D0
D0
(This specification is subject to change without further notice)
CSB
CSB
CSB
CSB
1.5kHz × 8
1.5kHz × 4
1.5kHz × 2
0
0
0
0
1.5kHz
Product Specification (V1.0) 08.04.2005
RS
RS
RS
RS
1
1
1
1
RDB WRB RE2
RDB WRB RE2
RDB WRB RE2
RDB WRB RE2
1
1
0
1
0
0
0
1
0/1
1
1
1
RE1
RE1
RE1
RE1
0/1
0
0
0
RE0
RE0
RE0
RE0
0/1
1
0
1