AZ100LVEL16VR_12 AZM [Arizona Microtek, Inc], AZ100LVEL16VR_12 Datasheet - Page 4

• Manufacturer Part Number: AZ100LVEL16VR_12
• Description: PECL/ECL Oscillator Gain Stage & Buffer with Selectable Enable
• Manufacturer: AZM [Arizona Microtek, Inc]

Arizona Microtek, Inc.
Figure 3 illustrates the timing sequences for the AZ100LVEL16VR in the MLP 16 package or as die. It is shown here
with the enable operating in active Low mode with a PECL threshold. This mode is determined by leaving the EN-SEL
open (NC). An active High enable with a CMOS/TTL threshold is also an option.
F
A CMOS enable input (EN) allows continuous oscillator operation. When the EN input is HIGH or left open (NC), the Q ¯
and Q
low while Q ¯ continues to follow the data input. The Q ¯ output has an internal 4 mA current source to V
eliminating the need for an external pull-down resistor.
The AZ100LVEL16VRNEG also provides biasing. Data input D is tied to the VBB pin through a 470Ω internal bias
resistor while the inverting input D ¯ is connected directly to V
should be bypassed to ground with a 0.01 µF capacitor.
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UNCTIONALITY
HG
/Q ¯
HG
outputs follow the data input. When EN is LOW, the Q
MLP 8 P
ACKAGE
D
EN
Q
Q
D
Q
Q
Q
EN
Q
Q
Figure 4 - AZ100LVEL16VRNEG Timing Diagram
HG
HG
HG
HG
Figure 3 - AZ100LVEL16VRL Timing Diagram
(AZ100LVEL16VRNEG)
(CMOS)
(PECL)
AZ100LVEL16VR
4
BB
. The V
HG
output is forced high and the Q ¯
BB
pin supports 1.5mA sink/source current. V
PECL/ECL Oscillator Gain Stage
& Buffer with Selectable Enable
May 2012, Rev 2.0
HG
EE
output is forced
, in most cases
BB