CH7008A-V ETC [List of Unclassifed Manufacturers], CH7008A-V Datasheet - Page 9
CH7008A-V
Manufacturer Part Number
CH7008A-V
Description
Digital PC to TV Encoder Features
Manufacturer
ETC [List of Unclassifed Manufacturers]
Datasheet
1.CH7008A-V.pdf
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CHRONTEL
When IDF = 9, (YCrCb 8-bit mode), H and V sync signals can be embedded into the data stream. In this mode, the
embedded sync will be similar to the CCIR656 convention, and the first byte of the ‘video timing reference code’
will be assumed to occur when a Cb sample would occur – if the video stream was continuous. This is delineated in
Table 6 shown below.
In this mode, the S[7:0] byte contains the following data:
S[6]
S[5]
S[4]
Bits S[7] and S[3-0] are ignored.
Table 6. YCrCb Multiplexed Mode with Embedded Syncs
201-0000-027 Rev 2.2, 9/30/99
Pixel#
Bus Data
Format
IDF#
=
=
=
F
V
H
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
=
=
=
P0a
1
1
1
1
1
1
1
1
1 during field 2, 0 during field 1
1 during field blanking, 0 elsewhere
1 during EAV (the synchronization reference at the end of active video)
0 during SAV (the synchronization reference at the start of active video)
P0b
0
0
0
0
0
0
0
0
P1a
0
0
0
0
0
0
0
0
P1b
S[7]
S[6]
S[5]
S[4]
S[3]
S[2]
S[1]
S[0]
YCrCb 8-bit
9
P2a
Cb2[7]
Cb2[6]
Cb2[5]
Cb2[4]
Cb2[3]
Cb2[2]
Cb2[1]
Cb2[0]
P2b
Y2[7]
Y2[6]
Y2[5]
Y2[4]
Y2[3]
Y2[2]
Y2[1]
Y2[0]
P3a
Cr2[7]
Cr2[6]
Cr2[5]
Cr2[4]
Cr2[3]
Cr2[2]
Cr2[1]
Cr2[0]
CH7008A
P3b
Y3[7]
Y3[6]
Y3[5]
Y3[4]
Y3[3]
Y3[2]
Y3[1]
Y3[0]
9
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