H6006 EMMICRO [EM Microelectronic - MARIN SA], H6006 Datasheet - Page 6

• Manufacturer Part Number: H6006
• Description: Failsafe Watchdog
• Manufacturer: EMMICRO [EM Microelectronic - MARIN SA]

Monitoring of the unregulated voltage require versions B1,
A2 and B2. The versions are based on the principle that V
rises with V
time after V
has a 100 k Ω nominal resistance from V
voltage divider). The versions A2, B2, A3 and B3 have high
impedance V
threshold voltage programming by a voltage divider on pin
V
V
Specifications).
Timer Programming
With pin RC unconnected, the on-chip RC oscillator together
with its divider chain give a timeout T
For programming a different T
calculating component values is given by the formula:
Thus, a resistor decreases and a capacitor increases the
interval to timeout. By using both external components,
excellent temperature stability of T
period 2 x T
and watchdog timer run so long as the chip is powered with
at least the minimum positive supply voltage specified (V
and so long as V
power-up sequence. If the timer function is not required,
input TCL should be tied to output TO to give a simple
voltage monitor (see Fig. 14).
Typical Applications
Copyright © 2004, EM Microelectronic-Marin SA
TCL tied to either V
T
IN.
SH
TO
, V
The levels obtained are proportional to the internal levels
=~ 30 ms
SL
R
If R
1
IN
and V
min. = 10 kΩ, C
T
IN
1
TO
Latched
Address Bus
TO
starts dropping on power-down. The version B1
IN
is in MΩ and C
R
on power-up and V
is generated at the output TO . The oscillator
inputs (see Fig. 7 and Table 4) for external
=
⎡
⎢
⎢
⎢
⎢
⎣
0.75
RL
IN
Monitored
Voltage
remains above the level V
Decoder
DD
on the chip itself (see Electrical
Adress
+
Microprocessor
5.5
or V
(32
1 max
1
+
+
in pF, T
SS,
V
C
. = 1 µF
DD
SEL
RD
1
a precise square wave of
)
TO
R
•
DD
TO
−
1
, an approximation for
1.6
R
0.8
TO
1
can be achieved. With
holds up for a certain
TO
= 470 kΩ
220 pF
⎤
⎥
⎥
⎥
⎥
⎦
will be in ms.
C
•
of typically 10 ms.
1
IR 2
RESET
IR 1
IN
1.024
=
to V
SS
RL
(internal
after a
>9 V
ON
DD
),
Regulator
Voltage
6
Timer Clearing and RES Action
A negative edge or a negative pulse at the TCL input
longer than 150 ns will reset the timer and set TO high. If
a further TCL signal edge or pulse is applied before T
timeout, TO will stay high and the timer will again be reset
to zero (see Fig. 5). If no TCL signal is applied before the
T
period 2 x T
applied during the first low state of TO , then the RES
output will go low and stay low until the next TCL signal,
or until a fresh power-up sequence.
Combined Voltage and Timer Action
The combination of voltage and timer action is illustrated by
the sequence of events shown in Fig. 6. One timeout period
after V
high. No TCL pulse will have any effect until this power-on
reset delay is completed. After completing the power-up
sequence the watchdog timer starts acting. If no TCL pulse
occurs, the timeout warning TO goes active low after one
timeout period T
without a timer clear pulse TCL , TO changes its polarity
providing a square wave signal. RES activates at the end
of the first low state of the TO signal. A TCL pulse clears
the watchdog timer and resets the TO and RES output
inactive high again. A voltage drop below the V
overrides the timer and immediately forces RES and
has no effect until the next power-up sequence has
complete
V
V
TCL
RC
SAVE active low and disables TO . Any further TCL pulse
TO
IN
SS
timeout, TO will start to generate a square wave of
IN
reached V
SAVE
TO
RES
V
TO
starting with a low state. If no TCL signal is
DD
TO
. After each subsequent timeout period
SH
, during power-up, RES goes inactive
CS Disable
5 V
www.emmicroelectronic.com
RAM
H6006
Fig. 11
RL
level
TO