AS28F128J3MPBG-15/ET AUSTIN [Austin Semiconductor], AS28F128J3MPBG-15/ET Datasheet

AS28F128J3MPBG-15/ET

Manufacturer Part Number

AS28F128J3MPBG-15/ET

Description

Plastic Encapsulated Microcircuit 128Mb, x8 and x16 Q-FLASH Memory Even Sectored, Single Bit per Cell Architecture

Manufacturer

AUSTIN [Austin Semiconductor]

Datasheet

1.AS28F128J3MPBG-15ET.pdf (8 pages)

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Plastic Encapsulated Microcircuit

128Mb, x8 and x16 Q-FLASH Memory

Even Sectored, Single Bit per Cell Architecture

Features

For in-depth functional product detail and Timing Diagrams,

please reference Micron’s full product Datasheet:

General Description

ASI’s, AS28F128J3M Enhanced or Mil-Temp variant of Micron’s

Q-Flash family of devices, is a nonvolatile, electrically block-

erasable (FLASH), programmable memory device manufactured

using Micron’s 0.15um process technology.

containing 134,217,728 bits organized as either 16,777,218 (x8)

or 8,388,608 bytes (x16). The device is uniformly sectored with

one hundred and twenty eight 128KB ERASE blocks.

AS28F128J3MRG

Revision 5.0 11/23/04

100% Pin and Function compatible to Intel’s MLC Family

NOR Cell Architecture

2.7V to 3.6V VCC

2.7V to 3.6V or 5V VPEN (Programming Voltage)

Asynchronous Page Mode Reads

Manufacturer’s ID Code:

! MT28F128J3MRG

Industry Standard Pin-Out

Fully compatible TTL Input and Outputs

Common Flash Interface [CFI]

Scalable Command Set

Automatic WRITE and ERASE Algorithms

5.6us per Byte effective programming time

128 bit protection register

! 64-bit unique device identifier

! 64-bit user programmable OTP cells

Enhanced data protection feature with use of VPEN=VSS

Security OTP block feature

100,000 ERASE cycles per BLOCK

Automatic Suspend Options:

! Block ERASE SUSPEND-to-READ

! Block ERASE SUSPEND-to-PROGRAM

! PROGRAM SUSPEND-to-READ

Available Operating Ranges:

! Enhanced

! Mil-Temperature [-XT]

MT28F640J3

[-ET]

Rev. L Dated 04/16/04

Austin Semiconductor, Inc. reserves the right to change products or modify product specifications with appropriate notification

For Additional Products and Information visit out Web site at

Micron

-40

-55

C to +105

C to +125

Austin Semiconductor, Inc.

This device

0x2Ch

This device features in-system block locking. They also have a

Common FLASH Interface [CFI] that permits software algorithms

to be used for entire families of devices. The software is device-

independent, JEDEC ID-independent with forward and backward

compatibility.

A22

CE1

CE0

A21

A20

A19

A18

A17

A16

VCC

A15

A14

A13

A12

VPEN

RP\

A11

A10

VSS

www.austinsemiconductor.com

BYTE\

DQ8

A23

CE2

DNU

VSS

DQ1

DQ0

PIN ASSIGNMENT

DQ10

DQ2

DQ9

VCC

A10

A11

64-Ball FBGA

VPEN

VCCQ

DQ3

DQ11 DQ12

CE0

VSS

A12

RP\

DQ13

DQ5

DNU

DQ4

A13

A14

A15

DNU

VSS

VCC

A25

DNU

DQ6

DQ15

DQ14

DNU

A16

DQ7

A18

A19

A20

AS28F128J3M

STS

WE\

CE1

OE\

A24

A22

A21

A17

Q-Flash

PEM

DQ5

WE\

OE\

STS

DQ15

DQ7

DQ14

DQ6

VSS

DQ13

DQ12

DQ4

VCCQ

VSS

DQ11

DQ3

DQ10

DQ2

VCC

DQ9

DQ1

DQ8

DQ0

BYTE\

A23

CE2

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AS28F128J3MPBG-15/ET Summary of contents

Page 1

Plastic Encapsulated Microcircuit 128Mb, x8 and x16 Q-FLASH Memory Even Sectored, Single Bit per Cell Architecture Features 100% Pin and Function compatible to Intel’s MLC Family NOR Cell Architecture 2.7V to 3.6V VCC 2. VPEN (Programming ...

Page 2

Functional Block Diagram: I/O CNTL Logic ADDR Buffer/ Latch Power (Current) Control CEx OE\ Command WE\ Execution Logic RP\ [CEL] WP\ CLK STS VPEN WAIT Additionally, the Scaleable Command Set [SCS] allows a single, simple software driver in all host ...

Page 3

Three Chip Enable (CEx) pins are used for enabling and disabling the device by activating the device’s control logic, input buffer, decoders, and sense amplifiers. BYTE\ enables the device to be used x16 configuration. Byte=Low (logic 0) ...

Page 4

Bus Operations: MODE RP\ CE0 CE1 Read Array VIH Enabled Enabled Output Disable VIH Enabled Enabled Standby VIH Disabled Disabled Reset/Power-Down VIL X X Read Identifier Codes VIH Enabled Enabled Read Query VIH Enabled Enabled Read Status (ISM off) VIH ...

Page 5

Memory Command Set Operations: Scalable or Basic Command Command Set [SCS or BCS] READ ARRAY READ IDENTIFIER CODES READ QUERY READ STATUS REGISTER CLEAR STATUS REGISTER WRITE TO BUFFER WORD/BYTE PROGRAM BLOCK ERASE BLOCK ERASE/PROGRAM SUSPEND BLOCK ERASE/PROGRAM RESUME CONFIGURATION ...

Page 6

AC Switching Characteristics: (VDD=3.0V –5%/+10%, TA= Min. / Max. temperatures of Operational Range chosen) Parameter Write Operations RP\ High Recovery to WE\ (CEx) going Low CEx (WE\) Low to WE\ (CEx) going High Write Pulse Width Data Setup to WE\ ...

Page 7

Mechanical Diagram TSOP, Type I, 56 Pin (Dimensions in mm) 0.15 +0.03, -0.02 AS28F128J3MRG Austin Semiconductor, Inc. reserves the right to change products or modify product specifications with appropriate notification Revision 5.0 11/23/04 For Additional Products and Information visit out ...

Page 8

... ASI Ordering Information ASI Part Number Enhanced Operating Range (-40 AS28F128J3MRG-15/ET AS28F128J3MPBG-15/ET Extended Operating Range (-55 AS28F128J3MRG-15/XT AS28F128J3MPBG-15/XT AS28F128J3MRG Austin Semiconductor, Inc. reserves the right to change products or modify product specifications with appropriate notification Revision 5.0 11/23/04 For Additional Products and Information visit out Web site at Austin Semiconductor, Inc ...

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