89C51IC2-CM ATMEL [ATMEL Corporation], 89C51IC2-CM Datasheet - Page 67

• Manufacturer Part Number: 89C51IC2-CM
• Description: 8-bit Flash Microcontroller with 2-wire Interface
• Manufacturer: ATMEL [ATMEL Corporation]

Power Management
Reset
Cold Reset
4301A–8051–01/04
Two power reduction modes are implemented in the AT89C51IC2: the Idle mode and
the Power-down mode. These modes are detailed in the following sections. In addition
to these power reduction modes, the clocks of the core and peripherals can be dynami-
cally divided by 2 using the X2 mode detailed in Section “Enhanced Features”.
In order to start-up (cold reset) or to restart (warm reset) properly the microcontroller, an
high level has to be applied on the RST pin. A bad level leads to a wrong initialization of
the internal registers like SFRs, Program Counter… and to unpredictable behavior of
the microcontroller. A proper device reset initializes the AT89C51IC2 and vectors the
CPU to address 0000h. RST input has a pull-down resistor allowing power-on reset by
simply connecting an external capacitor to V
be applied either directly on the RST pin or indirectly by an internal reset source such as
the watchdog timer. Resistor value and input characteristics are discussed in the Sec-
tion “DC Characteristics” of the AT89C51IC2 datasheet.
Figure 23. Reset Circuitry and Power-On Reset
2 conditions are required before enabling a CPU start-up:
•
•
If one of these 2 conditions are not met, the microcontroller does not start correctly and
can execute an instruction fetch from anywhere in the program space. An active level
applied on the RST pin must be maintained till both of the above conditions are met. A
reset is active when the level V
period of time where V
taken into account to determine the reset pulse width:
•
•
To determine the capacitor value to implement, the highest value of these 2 parameters
has to be chosen. Table 1 gives some capacitor values examples for a minimum R
50 K and different oscillator startup and V
V
The level on X1 input pin must be outside the specification (V
V
Oscillator startup time.
RST
DD
DD
must reach the specified V
rise time,
RST input circuitry
VDD
VSS
P
DD
and the oscillator are not stabilized. 2 parameters have to be
IH1
DD
is reached and when the pulse width covers the
range
DD
DD
rise times.
From Internal
Reset Source
To CPU Core
and Peripherals
as shown in Figure 23. A warm reset can
AT89C51IC2
IH
Power-on Reset
, V
VDD
IL
+
)
RST
RST
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