SED1565 EPSON [Epson Company], SED1565 Datasheet - Page 75

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SED1565

Manufacturer Part Number
SED1565
Description
Direct display of RAM data through the display data RAM
Manufacturer
EPSON [Epson Company]
Datasheet
Address hold time
Address setup time
System cycle time
Control L pulse width (WR)
Control L pulse width (RD)
Control H pulse width (WR)
Control H pulse width (RD)
Data setup time
Address hold time
RD access time
Output disable time
Address hold time
Address setup time
System cycle time
Control L pulse width (WR)
Control L pulse width (RD)
Control H pulse width (WR)
Control H pulse width (RD)
Data setup time
Address hold time
RD access time
Output disable time
*1 The input signal rise time and fall time (
*2 All timing is specified using 20% and 80% of V
*3
extremely fast, (
t
at the “L” level.
CCLW
Item
Item
and
t
CCLR
t
are specified as the overlap between CS1 being “L” (CS2 = “H”) and WR and RD being
r
+
t
f
)
(
t
D0 to D7
D0 to D7
CYC8
Signal
Signal
WR
WR
WR
WR
RD
RD
RD
RD
A0
A0
A0
A0
t
CCLW
Symbol
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
AH8
AW8
CYC8
CCLW
CCLR
CCHW
CCHR
DS8
DH8
ACC8
OH8
AH8
AW8
CYC8
CCLW
CCLR
CCHW
CCHR
DS8
DH8
ACC8
OH8
r
,
t
t
f
) is specified at 15 ns or less. When the system cycle time is
CCHW
EPSON
Table 27
Table 28
DD
) for (
as the reference.
C
C
t
Condition
Condition
r
L
L
+
= 100 pF
= 100 pF
t
f
)
(V
(V
(
t
DD
DD
CYC8
= 2.7 V to 4.5 V, Ta = –40 to 85 C )
= 1.8 V to 2.7 V, Ta = –40 to 85 C )
t
CCLR
1000
Min
300
120
Min
120
240
120
120
60
60
60
40
15
10
80
30
10
0
0
0
0
Rating
Rating
t
CCHR
SED1565 Series
Max
Max
140
100
280
200
) are specified.
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
8–73

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