EP910 ALTERA [Altera Corporation], EP910 Datasheet - Page 28

• Manufacturer Part Number: EP910
• Description: The Altera Classic device family offers a solution to high-speed, lowpower logic integration. Fabricated on advanced CMOS technology
• Manufacturer: ALTERA [Altera Corporation]

Classic EPLD Family Data Sheet
772
t
t
t
t
t
f
t
t
t
t
t
t
f
t
t
t
t
t
t
t
f
Symbol
PD1
PD2
PZX
PXZ
CLR
MAX
SU
H
CH
CL
CO1
CNT
CNT
ASU
AH
ACH
ACL
ODH
ACO1
ACNT
ACNT
Table 19. EP910 External Timing Parameters
Input to non-registered output
I/O input to non-registered output
Input to output enable
Input to output disable
Asynchronous output clear time
Maximum frequency
Global clock input setup time
Global clock input hold time
Global clock high time
Global clock low time
Global clock to output delay
Global clock minimum clock period
Maximum internal global clock
frequency
Array clock input setup time
Array clock input hold time
Array clock high time
Array clock low time
Output data hold time after clock
Array clock to output delay
Array clock minimum clock period
Maximum internal array clock
frequency
Parameter
Tables 19
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 5 pF
C1 = 35 pF
(5)
C1 = 35 pF
(6)
(6)
C1 = 35 pF
C1 = 35 pF
(6)
Conditions
and
20
(4)
Notes (1), (2)
(7)
show the timing parameters for EP910 devices.
Min Max Min Max Min Max
41.7
24.0
12.0
12.0
33.3
10.0
15.0
15.0
15.0
33.3
EP910-30
0.0
1.0
30.0
33.0
30.0
30.0
33.0
30.0
33.0
30.0
18
37.0
27.0
13.0
13.0
28.6
10.0
15.0
16.0
16.0
28.6
EP910-35
0.0
1.0
35.0
38.0
35.0
35.0
38.0
21.0
35.0
38.0
35.0
32.3
31.0
15.0
15.0
25.0
10.0
15.0
17.0
17.0
25.0
EP910-40
0.0
1.0
40.0
43.0
40.0
40.0
43.0
24.0
40.0
43.0
40.0
Altera Corporation
Adder
Turbo
Non-
30.0
30.0
30.0
30.0
30.0
30.0
30.0
30.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
(3)
Unit
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns