OV7661 OmniVision, OV7661 Datasheet
OV7661
Related parts for OV7661
OV7661 Summary of contents
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... All required image processing functions, including exposure control, gamma, white balance, color saturation, hue control and more, are also programmable through the SCCB interface. In addition, OmniVision use proprietary sensor technology to ...
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... SCCB Interface • Digital Video Port Figure 2 Functional Block Diagram Analog Processing Column Sense Amp Image Array (664 x 492) Clock Video Timing Generator XCLK1 HREF PCLK VSYNC 2 Proprietary to OmniVision Technologies AMERA HIP G A Exposure/Gain Detect Exposure/Gain Control RESET PWDN Video DSP Formatter ...
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... Register bits COM2[1:0] increase I and can be adjusted as a function of the customer’s loading. SCCB Interface The Serial Camera Control Bus (SCCB) interface controls the C AMERA Technologies Serial Camera Control Bus (SCCB) Specification Proprietary to OmniVision Technologies Functional Description /I drive current operation. Refer to ...
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... XCLK1 E3 DOGND D[7:0] for 8-bit YUV or RGB (D[7] MSB, D[0] LSB) b. Input (0) represents an internal pull-down resistor. 4 Proprietary to OmniVision Technologies AMERA HIP Power Analog power supply (+2.5 VDC) Power Analog ground Input SCCB serial interface clock input Output YUV/RGB video component output bit[1] Output YUV/RGB video component output bit[3] Reference voltage - connect to ground using a 0.1 µ ...
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... A Condition – – – a See Note b See Note CMOS 0 CMOS 0 See Note GND to V DD-IO = 2.5V = 24MHz at 7.5 fps YUV output, no I/O loading CLK = 2.5V refers to a PWDN pin-initiated Standby DDS:PWDN Proprietary to OmniVision Technologies Electrical Characteristics +1V DD-IO Min Typ Max 2.45 2.5 2.8 1.62 1.8 1.98 2.25 V +0.3V DD DD-IO 0 DD-IO DD-IO 0 ...
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... PHH PCLK[↓] to HREF[↓] t PHL • DD-C • Rise/Fall Times: I/O: AC Conditions: • Input Capacitance: 10pf • Output Loading: 25pF, 1.2KΩ to 2.5V • 24MHz CLK 6 Proprietary to OmniVision Technologies AMERA HIP < 70°C) A Parameter Figure 5, Figure 6, Figure = 1.8V 2.5V 2.5V DD-A DD-IO 5ns, Maximum SCCB: 300ns, Maximum O ...
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... SIO_D IN SIO_D OUT Figure 5 Horizontal Timing PCLK HREF Last Byte D[7:0] Version 1.91, January 24, 2005 t HIGH t LOW HD:STA HD:DAT SU:DAT PCLK t PHL (Row Data First Byte t PDV Proprietary to OmniVision Technologies Timing Specifications SU:STO t BUF t PHL Last Byte 7 ...
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... For Raw data, t For YUV/RGB, t Figure 8 QQVGA Frame Timing VSYNC LINE HREF HSYNC D[7:0] Invalid Data NOTE: For Raw data For YUV/RGB Proprietary to OmniVision Technologies AMERA HIP 510 x t LINE 480 x t LINE 11 t LINE t = 784 t LINE P 144 t P 640 t ...
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... LINE 608 t LINE P 256 t P 256t + 3t P LINE Row 0 Row 1 Proprietary to OmniVision Technologies Timing Specifications 25 t LINE 125 t P Invalid Data Row 287 25 t LINE 125 t P Invalid Data Row 143 LINE 125 t P Invalid Data ...
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... Figure 12 RGB 565 Output Timing Diagram PCLK HREF Last Byte D[7:0] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Figure 13 RGB 555 Output Timing Diagram PCLK HREF Last Byte D[7:0] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] 10 Proprietary to OmniVision Technologies AMERA HIP t PCLK t PHL (Row Data First Byte t PDV First Byte Second Byte ...
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... O mni ision OV7660/OV7161 Light Response Figure 14 OV7660/OV7161 Light Response Version 1.91, January 24, 2005 Proprietary to OmniVision Technologies Timing Specifications 11 ...
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... BAVE 00 06 GEAVE 00 07 AECHH 00 08 RAVE 00 12 Proprietary to OmniVision Technologies AMERA HIP R/W AGC – Gain control gain setting RW • Range: [00] to [7F] AWB – Blue channel gain setting RW • Range: [00] to [FF] AWB – Red channel gain setting RW • Range: [00] to [FF] ...
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... Single frame output (used for Frame Exposure mode only) Common Control 4 RW Bit[7:0]: Reserved Common Control 5 Bit[7]: System clock selection. If the system clock is 48 MHz, this RW bit should be set to high to get a higher frame rate Bit[6:0]: Reserved Proprietary to OmniVision Technologies Register Set Description 13 ...
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... Name (Hex) 0F COM6 43 10 AECH 40 11 CLKRC 00 12 COM7 00 14 Proprietary to OmniVision Technologies AMERA HIP R/W Common Control 6 Bit[7]: Output of optical black line option 0: Disable HREF at optical black 1: Enable HREF at optical black Bit[6]: BLC input selection 0: Use electrical black line as BLC signal ...
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... Reserved Output Format - Horizontal Frame (HREF column) start high 8-bit (low RW 3 bits are at HREF[2:0]) Output Format - Horizontal Frame (HREF column) end high 8-bit (low RW 3 bits are at HREF[5:3]) Proprietary to OmniVision Technologies Register Set Description (0x9D) or BD60ST (0x9E) must be set ...
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... ROS 80 24 AEW 78 25 AEB 68 16 Proprietary to OmniVision Technologies AMERA HIP R/W Output Format - Vertical Frame (row) start high 8-bit (low 2 bits are at RW VREF[1:0]) Output Format - Vertical Frame (row) end high 8-bit (low 2 bits are at RW VREF[3:2]) Data Format - Pixel Delay Select (delays timing of the D[7:0] data relative ...
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... HREF Control Bit[7:6]: HREF edge offset to data output RW Bit[5:3]: HREF end 3 LSB (high 8 MSB at register HSTOP) Bit[2:0]: HREF start 3 LSB (high 8 MSB at register HSTART) Array Current Control RW Bit[7:0]: Reserved Array Reference Control RW Bit[7:0]: Reserved – Reserved Proprietary to OmniVision Technologies Register Set Description 17 ...
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... Default (Hex) Name (Hex) 37 ADC 04 38 ACOM 12 39 OFON 00 3A TSLB 0C 18 Proprietary to OmniVision Technologies AMERA HIP R/W ADC Control Bit[7:4]: Reserved Bit[3]: ADC range adjustment 0: 1x range RW 1: 1.5x range Bit[2:0]: ADC range adjustment 000: 0.8x 100: 1x 111: 1.2x ADC and Analog Common Mode Control ...
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... Bit[3]: Enable Y channel delay option Bit[2:0]: Output Y/UV delay Common Control 14 RW Bit[7:0]: Reserved Edge Enhancement Adjustment Bit[7:2]: Edge enhancement threshold[7:2] RW Bit[1:0]: Edge enhancement factor[3:2] (see register DSPC2[7:6] for Edge enhancement factor[1:0]) Proprietary to OmniVision Technologies Register Set Description ADVFL will be automatically updated. 19 ...
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... MTX9 40 58 MTXS 0F 59-61 RSVD XX 20 Proprietary to OmniVision Technologies AMERA HIP R/W Common Control 15 Bit[7:6]: Data format - output full range enable 0x: Output range: [10] to [F0] 10: Output range: [01] to [FE] 11: Output range: [00] to [FF] RW Bit[5:4]: RGB 555/565 option (must set COM7[ and COM7[ ...
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... BD60ST 7F 9F RSVD XX A0 DSPC2 00 A1-A5 RSVD XX NOTE: All other registers are factory-reserved. Please contact OmniVision Technologies for reference register settings. Version 1.91, January 24, 2005 R/W RW Lens Correction Option 1 RW Lens Correction Option 2 RW Lens Correction Option 3 RW Lens Correction Option 4 Lens Correction Control ...
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... Ball Diameter Total Pin Count Pin Count X-axis Pin Count Y-axis Pins Pitch X-axis Pins Pitch Y-axis Edge-to-Pin Center Distance Analog X Edge-to-Pin Center Distance Analog Y 22 Proprietary to OmniVision Technologies AMERA HIP for the array center on the chip ...
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... As most optical assemblies invert and mirror the image, the chip is typically mounted with pins oriented down on the PCB. Version 1.91, January 24, 2005 2755 µm 2049 µm Sensor Array OV7660/OV7161 Proprietary to OmniVision Technologies Package Specifications Array Center (189.8 µm, 189.3 µm) 23 ...
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... Environmental Specifications Table 8 OV7660/OV7161 Reliability Test Results Parameter Temperature/Humidity Temperature Cycling (Air-to-Air) Highly Accelerated Stress Test (HAST) High Temperature Storage (HTS) High Temperature Static Bias (HTSB) a. Pre-Condition (Moisture Level II): 125°C, 24h 24 Proprietary to OmniVision Technologies AMERA HIP 1.1 1.6 2 118 ...
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... OmniVision web site (http://www.ovt.com) to obtain the current versions of all documentation. • OmniVision Technologies, Inc. reserves the right to make changes to their products or to discontinue any product or service without further notice (It is advisable to obtain current product documentation prior to placing orders). • ...
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... Proprietary to OmniVision Technologies AMERA HIP Version 1.91, January 24, 2005 O mni ision ...