HY5DU561622CTP-28 HYNIX [Hynix Semiconductor], HY5DU561622CTP-28 Datasheet - Page 26

• Manufacturer Part Number: HY5DU561622CTP-28
• Description: 256M(16Mx16) gDDR SDRAM
• Manufacturer: HYNIX [Hynix Semiconductor]

Rev. 0.5 / Feb. 2006
AC CHARACTERISTICS - I
Row Cycle Time
(Manual Precharge)
Row Cycle Time
(Auto Precharge)
Auto Refresh Row Cycle Time
Row Active Time
Row Address to Column Address Delay
Row Active to Row Active Delay
Column Address to Column Address Delay t
Row Precharge Time
Last Data-In to Precharge Delay
(Write Recovery Time : tWR)
Last Data-In to Read Command
Auto Precharge Write Recovery +
Precharge Time
System Clock Cycle Time
Clock High Level Width
Clock Low Level Width
Data-Out edge to Clock edge Skew
DQS-Out edge to Clock edge Skew
DQS-Out edge to Data-Out edge Skew
Data-Out hold time from DQS
Clock Half Period
Data Hold Skew Factor
Input Setup Time
Input Hold Time
Write DQS High Level Width
Write DQS Low Level Width
Clock to First Rising edge of DQS-In
Data-In Setup Time to DQS-In (DQ & DM) t
Parameter
CL = 4.0
CL = 3.0
(AC operating conditions unless otherwise noted)
t
tRC_APCG
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
RC
RFC
RAS
RCDRD
RCDWT
RRD
CCD
RP
DPL
DRL
DAL
CK
CH
CL
AC
DQSCK
DQSQ
QH
HP
QHS
IS
IH
DQSH
DQSL
DQSS
DS
Symbol
t
-t
HPmin
t
0.45
0.45
0.75
0.75
0.85
Min
-0.7
-0.7
min
CH/L
4.0
0.4
0.4
0.4
15
17
18
40
QHS
5
2
2
1
5
3
2
8
-
-
-
4
Max
0.55
0.55
1.15
70K
0.7
0.7
0.4
0.4
0.6
0.6
7.0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
t
-t
HPmin
t
0.45
0.45
0.75
0.75
0.75
Min
-0.7
-0.7
CH/L
min
5.0
0.4
0.4
0.4
40
12
14
14
QHS
4
2
2
1
4
3
2
7
-
-
-
5
Max
0.55
0.55
0.45
1.25
70K
0.5
0.6
0.6
7.0
0.7
0.7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1HY5DU561622CTP
t
-t
HPmin
t
0.45
0.45
0.75
0.75
Min
0.75
-0.7
-0.7
CH/L
min
6.0
0.4
0.4
0.4
11
11
12
40
QHS
4
2
2
1
4
3
2
6
-
-
-
6
Max
0.55
0.55
0.45
1.25
70K
0.5
0.6
0.6
7.0
0.7
0.7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Unit
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
1, 6
1, 5
6
2
2
3
26