MX631DW CMLMICRO [CML Microcircuits], MX631DW Datasheet - Page 2

• Manufacturer Part Number: MX631DW
• Description: LOW VOLTAGE SPM DETECTOR
• Manufacturer: CMLMICRO [CML Microcircuits]

© 1997 MX•COM, INC.
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
Low Voltage SPM Detector
Pin
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
Xtal/Clock : The input to the on-chip clock oscillator; for use with a 3.579545MHz Xtal in
conjunction with the Xtal output (see Figure 2). Circuit components are on-chip. Using this mode of
clock operation, the Clock Out pin should be connected directly to the Clock In pin. If a clock pulse
input is employed to the Clock In pin, this pin must be connected directly to V
Xtal: The output of the on-chip clock oscillator inverter.
Clock Out: The buffered output of the on-chip clock oscillator inverter. If a Xtal input is employed
this output should be connected directly to the Clock In pin.
Clock In: The 3.579545MHz clock pulse input to the internal clock-dividers. In the clock pulse input
mode the Xtal/Clock input (pin 1) should be connected to V
No internal connection, leave open circuit.
No internal connection, leave open circuit.
V
decoupled to V
V
Signal In (+):
Signal In (-):
Amp Out:
No internal connection, leave open circuit.
Tone Follower Output: This output provides a logic “0” (Low) for the period of a detected tone and
a logic “1” (High) for N
Packet Mode Output: A logic output that will be available after a cumulation of 40ms of 'good' tone
has been received. This packet tone follower will only respond when a tone frequency of sufficient
quality has been received for sufficient time, i.e. a cumulation of 40ms in any 48ms; short tone
bursts or breaks will be ignored. This output provides a logic “0” (Low) for a detected tone and a
logic “1” (High) for N
System: The logic input to select device operation to either 12kHz (logic “1” - High) or 16kHz (logic
“0” - Low) SPM systems. This input has an internal 1M
V
MX631 are dependent upon this supply. This pin should be decoupled to V
close to the pin.
Note that if this device is ‘line’ powered, the resulting supply must be stable. See notes on IC
Protection from high and spurious line voltages.
Function
BIAS
SS
DD
: Negative supply (GND).
: Positive supply. A single, stable power supply is required. Critical levels and voltages within the
: The output of the on-chip analog bias circuitry. Held internally at V
SS
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(see Figure 2).
The positive and negative inputs to, and the output from,
the input gain adjusting signal amplifier. Refer to Figure 4
for guidance on setting level sensitivities to national specifications,
and the selection of gain adjusting components.
OTONE
OTONE
detection. See Figure 6.
detection. See Figure 5.
2
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pullup resistor (12kHz).
DD
. (See Figure 2.)
DD
/2, this pin should be
SS
by a capacitor mounted
DD
(see Figure 2).
Doc.# 20480087.003
MX631