LC7941YC SANYO [Sanyo Semicon Device], LC7941YC Datasheet
LC7941YC
Related parts for LC7941YC
LC7941YC Summary of contents
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... Ordering number: EN 6157 Overview The LC7940YC and LC7941YC are segment driver ICs for driving large, dot matrix LCD displays. They read 4 – bit parallel or serial input, display data from a controller into an 80 bit latch, and then generate LCD drive signals – ...
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... LCD supply. Electrlcai Characterfstlcs ± 2°C,V Parameter Symbol HIGH–level input current LOW–level input current CDO HIGH–level output voltage CDO LOW–levef output voltage O1 to O80 driver ON resistance LC7940YC, LC7941YC Symbol T opr T stg 85°C, V – Conditions ...
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... Switching Characteristics ± 2°C,V Parameter Symbol CDO output delay time Switching Characteristics Waveform SDI DI1 to 3 LOAD CDO LC7940YC, LC7941YC Conditions CDI = – 3.3 MHz output load ; – ...
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... O70 O69 O68 O67 O66 O65 O64 O63 O62 O61 O60 O59 O58 O57 O56 O55 O54 O53 O52 O51 LC7940YC, LC7941YC O80 O79 O78 O77 O76 O75 O74 O73 O72 O71 O70 O69 O68 O67 LC7940YC O66 O65 O64 O63 ...
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... O43 356 44 O44 502 45 O45 650 46 O46 800 47 O47 952 48 O48 1106 49 O49 1262 50 O50 1420 LC7940YC, LC7941YC LC7940YC Pad Location chip size : 4.830 mm x 3.550 mm Y Pin_No. Name 2240 51 O51 2072 52 O52 1906 53 O53 1742 54 O54 1580 55 O55 1420 56 O56 ...
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... O38 356 44 O37 502 45 O36 650 46 O35 800 47 O34 952 48 O33 1106 49 O32 1262 50 O31 1420 LC7940YC, LC7941YC LC7941C Pad Location chip size : 4.830 mm x 3.550 mm Y Pin No. Name 2240 51 O30 2072 52 O29 1906 53 O28 1742 54 O27 1580 55 O26 1420 56 O25 ...
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... CDI 98 83 LOAD 97 84 SDI 96 85 DI3 95 86 DI2 94 87 D11 LC7940YC, LC7941YC 02 03 079 080 Level LCD Drive Circuit (80 bits Level Shifter (80 bits) DISP OFF 80 2nd Latch (80 bits) 80 1st Latch (80 bits Address Decoder 4 bits ...
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... 100 NC LC7940YC, LC7941YC I/O I LCD panel drive voltage output alternation control signal. I Data input mode select. 4–bit parallel input when HIGH, and serial input when LOW Cascade connection pin for extension segment drivers. Data is read out when HIGH. O Goes LOW after data is read out. Connected to the CDI input of the next chip. ...
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... Application Notes LCD Panel 1 LC7940YC, LC7941YC 1 641 2 642 159 799 160 800 161 801 162 802 319 959 320 960 321 961 322 962 479 1119 480 1120 481 1121 482 1122 639 1279 640 1280 No. 6157—9/13 ...
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... LCD Panel 2 LC7940YC, LC7941YC No. 6157—10/13 ...
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... The LC7942YC chips are cascaded by connecting DIO64 on chip I to DIO1 on chip 2. For a 100 register, O37 to O64 on chip 2 are left open. 2. The LC7940YC (or LC7941YC) chips are cascaded by connecting CDO on chip I to CDI on chip 2, and CDO on chip 2 to CDI on chip 3. CDI on chip I is tied to GND, and CDO on chip 3 is not used. This confi ...
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... Chip 1 data read 1 frame (240 bits) M LOAD CP 1,1 1,2 SDI 1st line data read 1frame (100 M #1 DIO1 LOAD 01 1,1 1 1,80 080 01 1,81 #2 1,160 080 01 1,161 #3 080 1,240 LC7940YC, LC7941YC --- 1,79 1,80 1,81 --- Chip 2 data read --- 1,239 1,240 2,1 --- 2nd line data read 240 bits) 2,1 --- 98,1 99,1 100,1 2,2 --- 98,2 99,2 100,2 2,80 --- 98,80 99,80 100,80 2,81 ...
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... If this timing data is sent, data elements (m, 229), (m, 230), (m+1, 229), (m+1. 230)... will not appear in the output (O69 and O70 on chip 3). This is because the LC7940YC (or LC7941YC) converts serial/parallel data LOAD m,1 SDI In this case, (m, 231) is output on O71 on chip 3, and (m, 232) on O72 on chip 3. However, these outputs are not connected to the panel and are, therefore, invalid. Specifi ...