HDSP-2301 HP [Agilent(Hewlett-Packard)], HDSP-2301 Datasheet - Page 17

• Manufacturer Part Number: HDSP-2301
• Description: Four Character 5.0 mm (0.20 inch) 5 x 7 Alphanumeric Displays
• Manufacturer: HP [Agilent(Hewlett-Packard)]

loop instead of the in-line code.
This program uses 5.4% + .93N%
of the microprocessor time for a 2
MHz clock. These programs uti-
lize a subroutine “LOAD” which is
called whenever the display mes-
sage is changed. This subroutine
executes in 10.2 ms and 7.5 ms
respectively for Figure 6 and Fig-
ure 7. The program in Figure 8
uses 7.6% + 1.35N% of the micro-
processor time for a 2 MHz clock.
A 50% reduction in the previously
described microprocessor times
can be achieved by using faster
versions of the 6800 and 8080A
microprocessors.
The ASCII to 5 x 7 dot matrix de-
coder used by the programs in
Figures 6, 7, and 8 is located
within the microprocessor pro-
gram. This decoder requires 640
bytes of storage to decode the 128
character ASCII set. The decoder
used by these controllers is for-
matted so that the first 128 bytes
contain column 1 information; the
next 128 bytes contain column 2
information, etc. Each byte of this
decoder is formatted such that D
through D
Row 1 display data respectively.
The data is coded so that a HIGH
bit will turn the corresponding 5 x
7 display dot ON. This decoder
table is shown in Figure 9. The
resulting 5 x 7 dot matrix display
font is shown in the HDSP-2471
data sheet.
Decoded Data Controller
The DECODED DATA CONTROL-
LER circuit schematic for a 32
character display is depicted in
Figure 10. The circuit is specifi-
cally designed for interface to an
8080A microprocessor. This cir-
cuit is designed to accept and
store in local memory all of the
display data for a 32 character
HDSP-2000 display (1120 bits).
0
contain Row 7 through
6
The microprocessor loads 160
bytes of display data into the two
1 K x 1 RAM’s via the 74165 paral-
lel in, serial out shift register.
Each byte of data represents one
column of display data. The
counter string automatically gen-
erates the proper address location
for each serial bit of data after ini-
tialization by MEM W, the
character address, and the desired
column. Once the loading is com-
plete, the counter sequentially
loads and displays each column
(224 bits) of data at a 90 Hz rate
(2 MHz input clock rate). The tim-
ing for this circuit is shown in
Figure 11. The software required
to decode a 32 character ASCII
string is shown in Figure 12. This
program decodes the 32 ASCII
characters into 160 bytes of dis-
play data which are then stored in
the controller. The program re-
quires about 6.6 ms, for a 2 MHz
clock, to decode and load the
message into the DECODED
DATA CONTROLLER. This pro-
gram also uses the same decoder
table as shown in Figure 9.
Coded Data Controller
The CODED DATA CONTROL-
LER (Figure 13) is designed to
accept ASCII coded data for stor-
age in a local 128 x 8 RAM. After
the microprocessor has loaded
the RAM, local scanning circuitry
controls the decoding of the
ASCII, the display data loading,
and the column select function.
With minor modification, the cir-
cuit can be utilized for up to 128
display characters. The RAM used
in this circuit is an MCM6810P
with the Address and Data inputs
isolated via 74LS367 tri-state buff-
ers. This allows the RAM to be
accessed either by the micropro-
cessor or by the local electronics.
The protocol is arranged such that
the microprocessor always takes
precedence over the local scan-
ning electronics. The “Write”
cycle timing for the CODED
DATA CONTROLLER is depicted
in Figure 14. This circuit, as with
the DECODED DATA CONTROL-
LER, requires no microprocessor
time once the local RAM has been
loaded with the desired data.
The circuit shown in Figure 13
shows a CODED DATA CON-
TROLLER designed for a 32
character HDSP-2000 alphanu-
meric display. The key waveforms
shown in Figure 15, labeled
and
analysis of this circuit. Label
the 1 MHz clock. Label
output of 7404 pin 2 which is the
inverted Q
Label
pin 6 which is the ANDed output
of 2Q
74393. The Motorola 6810 RAM
stores 32 bytes of ASCII data
which is continuously read, de-
coded, and displayed. The ASCII
data from the RAM is decoded by
the Motorola 6674 128 character
ASCII decoder. The 6674 decoder
has five column outputs which are
gated to the Data Input of the dis-
play via a 74151 multiplexer.
Strobing of the display is accom-
plished via the 74197, 74393, and
7490 counter string. The 74197 is
connected as a divide by 8
counter that sequentially selects
the seven rows within the 6674.
As shown by waveform
74197 also enables seven clock
cycles to be gated to the clock in-
put of the display. The 74393 is a
divide by 256 counter connected
so that the five lowest order out-
puts select each of the 32 ASCII
characters within the RAM. The
three highest order outputs deter-
mine the relationship between
load time and column on time.
When 2Q
9
B
, are shown to simplify the
, 2Q
is the output of the 7404
B
D
C
= 2Q
, and 2Q
output of the 74197.
C
= 2Q
D
of the
D
= 1 of the
is the
, the
,
is
,