HDSP-210X HP [Agilent(Hewlett-Packard)], HDSP-210X Datasheet - Page 12

• Manufacturer Part Number: HDSP-210X
• Description: Eight Character 5 mm and 7 mm Smart Alphanumeric Displays
• Manufacturer: HP [Agilent(Hewlett-Packard)]

UDC RAM and UDC Address
Register
Figure 3 shows the logic levels
needed to access the UDC RAM
and the UDC Address Register.
The UDC Address Register is
eight bits wide. The lower four
bits (D
of the 16 UDC locations. The
upper four bits (D
used. Once the UDC address has
been stored in the UDC Address
Register, the UDC RAM can be
accessed.
To completely specify a 5 x 7
character, eight write cycles are
required. One cycle is used to
store the UDC RAM address in the
UDC Address Register and seven
cycles are used to store dot data
in the UDC RAM. Data is entered
by rows and one cycle is needed
to access each row. Figure 4
shows the organization of a UDC
character assuming the symbol to
be stored is an “F.” A
to select the row to be accessed
and D
the row dot data. The upper three
bits (D
significant bit) corresponds to the
right most column of the 5 x 7
matrix and D
bit) corresponds to the left most
column of the 5 x 7 matrix.
Flash RAM
Figure 5 shows the logic levels
needed to access the Flash RAM.
The Flash RAM has one bit
associated with each location of
the Character RAM. The Flash
input is used to select the Flash
RAM while address lines A
ignored. Address lines A
used to select the location in the
Flash RAM to store the attribute.
D
flash attribute. D
the attribute and D
removes the attribute.
0
is used to store or remove the
0
0
-D
5
-D
-D
4
3
7
are used to transmit
) are used to select one
) are ignored. D
4
(most significant
0
4
= “1” stores
0
-D
= “0”
0
7
-A
) are not
2
0
-A
are used
3
0
-A
2
(least
are
4
are
Figure 4. Data to Load ""F'' into the UDC RAM.
C
O
L
1
D
1
1
1
1
1
1
1
IGNORED
0 = LOGIC 0; 1 = LOGIC 1; * = ILLUMINATED LED.
When the attribute is enabled
through bit 3 of the Control Word
and a “1” is stored in the Flash
RAM, the corresponding
character will flash at approxi-
Figure 3. Logic Levels to Access a UDC Character.
4
C
O
L
2
D
1
0
0
1
0
0
0
3
C
O
L
3
D
1
0
0
1
0
0
0
2
C
O
L
4
D
1
0
0
1
0
0
0
1
C
O
L
5
D
1
0
0
0
0
0
0
0
ROW 1
ROW 2
ROW 3
ROW 4
ROW 5
ROW 6
ROW 7
CHARACTER
* * * * *
*
*
* * * *
*
*
*
12
mately 2 Hz. The actual rate is
dependent on the clock frequency.
For an external clock the flash
rate can be calculated by dividing
the clock frequency by 28,672.
UDC
HEX
CODE
1F
10
10
1D
10
10
10