YMF754-V ETC, YMF754-V Datasheet - Page 29

• Manufacturer Part Number: YMF754-V
• Description: DS-1E
• Manufacturer: ETC

YMF754
b1................SPR1: Secondary AC’97 Power Down Control 1
b2................SPR2: Secondary AC’97 Power Down Control 2
b3................SPR3: Secondary AC’97 Power Down Control 3
b4................SPR4: Secondary AC’97 Power Down Control 4
b5................SPR5: Secondary AC’97 Power Down Control 5
b6................SPR6: Secondary AC’97 Power Down Control 6
b7................SPR7: Secondary AC’97 Power Down Control 7
Respective data set to b[7:0] are correspondingly set into the “Power down Ctrl/Stat” register in the
Secondary AC’97 via the AC-Link. These are not set into the “Power down Ctrl/Stat” register in the Primary
AC’97.
This bit controls the power state of the DAC in the Secondary AC’97.
This bit controls the power state of the Analog Mixer (Vref still on) in the Secondary AC’97. This
power state retains the Reference Voltage of the AC’97.
This bit controls the power state of the Analog Mixer (Vref off) in the Secondary AC’97. This power
state removes Reference Voltage of the AC’97.
This bit controls the power state of the AC-link in the Secondary AC’97.
Setting this bit to “1” disables the internal clock of the Secondary AC’97. In case the AC’97 is used with
DS-1E, the master clock is supplied from DS-1E. Therefore, when the clock is stopped completely, set
SPR5 bits to “1” firstly, then the CMCD bit should be set to “1” after duration of 1ms or longer.
This bit controls PR6 bit status of the power control register in the Secondary AC’97.
This bit controls PR7 bit status of the power control register in the Secondary AC’97.
“0”: Normal
“1”: Power down
“0”: Normal
“1”: Power down
“0”: Normal
“1”: Power down
“0”: Normal
“1”: Power down
“0”: Normal
“1”: Disable
(default)
(default)
(default)
(default)
(default)
-29-
June 28, 1999