YMF724 ETC, YMF724 Datasheet - Page 23
YMF724
Manufacturer Part Number
YMF724
Description
high performance audio controller for the PCI Bus
Manufacturer
ETC
Datasheet
1.YMF724.pdf
(50 pages)
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YMF724F
b12..............PR4: AC’97 Power down Control 4
b13..............PR5: AC’97 Power down Control 5
b[15:14] ......AC’97 Power down Control 6 and 7
This bit controls the power state of the AC-link in AC’97.
Setting this bit to “1” disables the internal clock of AC’97. In case AC’97 is used with DS-1, the master
clock is supplied from DS-1. Therefore, when the clock of AC’97 is stopped completely, set both PR5
and PSN bits to “1”.
These bits control PR6 and PR7 status of the power control register in AC’97.
- Set DPLL0, DPLL1, PSL0, PSL1 and PSN bits to “1”, when DMC bit is set to “1”.
- Set PSL0 and PSL1 bits to “1”, when DPLL0 bit is set to “1”.
- Set PSN bit to “1”, when DPLL1 bit is set to “1”.
“0”: Normal
“1”: Power down
“0”: Normal
“1”: Disable
(24.576MHz)
PCICLK
(33MHz)
Master
DMC
(default)
(default)
49.152MHz
33.87MHz
DPLL0
DPLL1
PLL1
PLL0
-23-
PSL0
PSL1
PSN
PCI func. 0
PCI func. 1
Legacy func. 0
Legacy func. 1
AC3F2 I/F
AC'97 I/F
H/W Vol.
PCI Audio
SRC
SPDIF
PCI I/F
PC/PCI
D-DMA
S-IRQ
FM Synthesizer
SB Pro
MPU401
Joystick
January 14, 1999