MX27C4111MC-10 MCNIX [Macronix International], MX27C4111MC-10 Datasheet - Page 4

• Manufacturer Part Number: MX27C4111MC-10
• Description: 4M-BIT [512K x8/256K x16] CMOS EPROM WITH PAGE MODE
• Manufacturer: MCNIX [Macronix International]

STANDBY MODE
The MX27C4111 has a CMOS standby mode which
reduces the maximum VCC current to 100 uA. It is
placed in CMOS standby when CE is at VCC ± 0.3 V.
The MX27C4111 also has a TTL-standby mode which
reduces the maximum VCC current to 1.5 mA. It is
placed in TTL-standby when CE is at VIH. When in
standby mode, the outputs are in a high-impedance
state, independent of the OE input.
TWO-LINE OUTPUT CONTROL FUNCTION
To accommodate multiple memory connections, a two-
line control function is provided to allow for:
It is recommended that CE be decoded and used as the
primary device-selecting function, while OE be made a
common connection to all devices in the array and
MODE SELECT TABLE
NOTES:
1.VH = 12.0V ± 0.5V
2.X = Either VIH or VIL
3.A1 - A8, A10 - A17 = VIL (For auto select)
4.See DC Programming Characteristics for VPP
P/N: PM0239
voltages.
1. Low memory power dissipation,
2. Assurance that output bus contention will not
occur.
MODE
Read (Word)
Read (Upper Byte)
Read (Lower Byte)
Output Disable
Standby
Program
Program Verify
Program Inhibit
Manufacturer Code(3)
Device Code(3)
CE
VIL
VIL
VIL
VIL
VIH
VIL
VIH
VIH
VIL
VIL
OE
VIL
VIL
VIL
VIH
X
VIH
VIL
VIH
VIL
VIL
A9
X
X
X
X
X
X
X
X
VH
VH
A0
X
X
X
X
X
X
X
X
VIL
VIH
4
5.BYTE/VPP is intended for operation under DC
6.Manufacture code = 00C2H
connected to the READ line from the system control
bus. This assures that all deselected memory devices
are in their low-power standby mode and that the output
pins are only active when data is desired from a
particular memory device.
SYSTEM CONSIDERATIONS
During the switch between active and standby
conditions, transient current peaks are produced on the
rising and falling edges of Chip Enable. The magnitude
of these transient current peaks is dependent on the
output capacitance loading of the device. At a minimum,
a 0.1 uF ceramic capacitor (high frequency, low inherent
inductance) should be used on each device between
Vcc and GND to minimize transient effects. In addition,
to overcome the voltage drop caused by the inductive
effects of the printed circuit board traces on EPROM
arrays, a 4.7 uF bulk electrolytic capacitor should be
used between VCC and GND for each eight devices.
The location of the capacitor should be close to where
the power supply is connected to the array.
Q15/A-1
Q15 Out
VIH
VIL
High Z
High Z
Q15 In
Q5 Out
High Z
0B
1B
Voltage conditions only.
Device code = B800H
BYTE/
VCC
GND
X
X
VPP
VPP
VPP
VCC
VCC
VPP(5)
GND
MX27C4111
Q8-14
Q8-14 Out
High Z
High Z
High Z
High Z
Q8-14 In
Q8-14 Out
High Z
00H
38H
REV. 2.7, NOV. 19, 2002
Q0-7
Q0-7 Out
Q8-15 Out
Q0-7 Out
High Z
High Z
Q0-7 In
Q0-7 Out
High Z
C2H
00H