MAS9116AAHV06 MAS [Micro Analog systems], MAS9116AAHV06 Datasheet - Page 6

• Manufacturer Part Number: MAS9116AAHV06
• Description: Stereo Digital Volume Control
• Manufacturer: MAS [Micro Analog systems]

TEST REGISTER CR5 DESCRIPTION
Note: Test register is intended only for internal testing of the device and not supposed to be used in
normal operation. It is strongly recommended not to change initial test register value (00hex).
XMUTE pin is output pin when bit 1 is set in register CR5. Bits 2, 3 and 4 select different internal signals. In test
phase those signals can be seen via XMUTE pin.
Condition
Note 1. Forces the new gain value to be latched to resistor network without waiting for zero crossing or delay generator. LSB bit has to be
returned to 0 before next gain value can be latched. When force latch is used, both channels are latched with the same value.
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed may cause permanent damage to the device. The device may not operate under these conditions, but it will not
be destroyed.
RECOMMENDED OPERATION CONDITIONS
Parameter
Signal Voltage
Positive Supply Voltage
Negative Supply Voltage
Signal Grounds
Operating Temperature
Parameter
Signal Voltage
Positive Supply Voltage
All other pins
Storage Temperature
Operating Temperature
ESD (HBM) pins 3, 4, 13 and 14
ESD (HBM) all other pins
Test, XMUTE=out
Test, XMUTE=out
Test, XMUTE=out
Test, XMUTE=out
Test, XMUTE=out
Test, XMUTE=out
Test, XMUTE=out
Test, XMUTE=out
Test, XMUTE=in
XMUTE=in
7
0
0
0
0
0
0
0
0
0
0
6
0
0
0
0
0
0
0
0
0
0
RIN, RFO, LIN, LFO
RIN, RFO, LIN,
AGND,DGND
LGND,RGND
AVCC,DVCC
AVCC, DVCC
5
0
0
0
0
0
0
0
0
0
0
Symbol
Symbol
LFO
Data Byte bits
TA
TS
TA
4
0
0
0
0
0
0
1
1
1
1
3
0
0
0
0
1
1
0
0
1
1
Conditions
(AVCC=+5.0 V, AVSS=0 V, TA=+25
2
0
0
0
1
0
1
0
1
0
1
Conditions
1
0
0
1
1
1
1
1
1
1
1
Min
-18
-20
4.5
0
0
1
0
0
0
0
0
0
0
0
right enable for zero crossing
left enable for zero crossing
2000
All voltages with respect to ground.
Min
-0.5
-0.3
300
-20
-55
-40
+25
Typ
right delay generator
5
0
0
and delay generator
and delay generator
left delay generator
Force latch, note 1
right peak detector
right zero crossing
Normal operation
left peak detector
left zero crossing
22 November, 2005
o
C unless otherwise noted)
AVCC +0.3
Function
+125
Max
+6.0
Max
+18
+60
+20
+85
DA9116.005
5.5
Unit
o
6 (18)
Unit
V
V
V
V
C
o
o
V
V
V
V
C
C