LC74900 SANYO [Sanyo Semicon Device], LC74900 Datasheet - Page 8

• Manufacturer Part Number: LC74900
• Description: CMOS IC Silicon gate LCD PROCESSOR LSI for small size display
• Manufacturer: SANYO [Sanyo Semicon Device]

Pin Functions
Pin
No.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1
2
3
4
5
6
7
8
9
ADC0AV DD 33
ADC1AV DD 33
ADC0AV SS 33
ADC1AV SS 33
PLLAV DD 33
PLLAV SS 33
SRXD_SDA
SCS_I2SEL
Pin symbol
SCK_SCL
REFNKV
DV DD 15
DV DD 33
REFPKV
XV DD 33
DV DD 15
DV DD 33
XPDWN
SIOSEL
MODE2
MODE3
MODE0
MODE1
DCBIN0
DCBIN1
DCBIN2
XMUTE
XTALO
DV SS
XTALI
XRST
STXD
TEST
LPFO
XV SS
DCKI
INTO
DDEI
DHSI
AIN4
AIN3
AIN2
AIN1
DVSI
VRB
SVO
PDO
GP0
GP1
GP2
VRT
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
P
P
P
P
P
P
P
P
P
P
P
P
P
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I/O format
Format
C
C
D
D
D
D
D
D
D
D
D
A
A
B
B
B
B
A
E
E
E
E
E
E
E
E
E
E
F
F
D
D
A
B
D
D
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Analog voltage
Analog voltage
Analog voltage
Core voltage
Core voltage
IO voltage
IO voltage
IO voltage
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
GND
GND
GND
GND
GND
Connected to
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
LC74900
IO power
DV DD 33
DV DD 33
DV DD 33
DV DD 33
DV DD 33
DV DD 33
DV DD 33
DV DD 33
DV DD 33
DV DD 33
DV DD 33
DV DD 33
DV DD 33
DV DD 33
DV DD 33
DV DD 33
DV DD 33
DV DD 33
DV DD 33
DV DD 33
DV DD 33
DV DD 33
DV DD 33
DV DD 33
XV DD 33
XV DD 33
Digital
supply
Power supply for core (1.5V)
Reset pin (active at a low voltage level)
Fixed at a high voltage level
Input: Digital input/OSD enable (pull down if not used)
Output: Global port/Video decoder Vsync
Input: Digital input/OSD halftone (pull down if not used)
Output: Global Port/Video DecoderHsync
Global port output
Power supply for IO (3.3V)
GND for digital
I
I
SPI: data output
I
Select CPU I/F, ”L”: I
Operation mode control
Operation mode control
For production test (Fixed at a low voltage level)
Top reference level Buffer-AMP input for ADC
Top reference level for ADC
Bottom reference level Buffer-AMP input for ADC
Bottom reference level for ADC
Power supply for ADC (3.3V)
CVBS input 4
GND for ADC
CVBS input 3
Power supply for ADC (3.3V)
CVBS input 2
GND for ADC
CVBS input 1
AFE output
External AGC control level
Power supply for PLL (3.3V)
Test port for PLL (Open)
GND for PLL
Power supply for 27MHz X’tal (3.3V)
27MHz X’tal input
27MHz X’tal output
GND for 27MHz X’tal
Power supply for core (1.5V)
Operation mode control
Digital video clock
Operation mode control
Mute control (active at a low voltage level)
Interrupt output
Digital video enable/OSD enable
Digital video Vsync/OSD half tone
Digital video Hsync
Power supply for IO (3.3V)
Digital video input/OSD input (pull down if not used)
Digital video input/OSD input (pull down if not used)
Digital video input/OSD input (pull down if not used)
2
2
2
C: I
C: data inout, SPI: data input
C: Select I
2
C Clock inout, SPI: Clock input
2
C slave address, SPI: Chip select
2
C, ”H”: SPI
Remarks
Continued on next page.
No.A2000-8/14