K9K1G08U0M-YIB0 Samsung semiconductor, K9K1G08U0M-YIB0 Datasheet - Page 3

• Manufacturer Part Number: K9K1G08U0M-YIB0
• Description: 128M x 8 Bit NAND Flash Memory
• Manufacturer: Samsung semiconductor

K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
Figure 2. Array Organization
Figure 1. Functional Block Diagram
V
V
(=8,192 Blocks)
CC
256K Pages
SS
NOTE : Column Address : Starting Address of the Register.
CE
RE
WE
2nd Cycle
1st Cycle
3rd Cycle
4th Cycle
Command
A
A
00h Command(Read) : Defines the starting address of the 1st half of the register.
01h Command(Read) : Defines the starting address of the 2nd half of the register.
* A
* L must be set to "Low".
* The device ignores any additional input of address cycles than reguired.
9
0
- A
8
- A
1st half Page Register
(=256 Bytes)
is set to "Low" or "High" by the 00h or 01h Command.
26
7
I/O 0
A
A
A
A
17
25
512B Bytes
0
9
& High Voltage
CLE
Page Register
Control Logic
512 Bytes
X-Buffers
Latches
& Decoders
Y-Buffers
Latches
& Decoders
Command
Generator
Register
I/O 1
A
A
A
A
ALE
10
18
26
1
2nd half Page Register
(=256 Bytes)
A
8
WP
I/O 2
A
A
A
* L
11
19
2
16 Bytes
16 Bytes
I/O 3
A
A
A
*L
12
20
3
3
I/O 4
A
A
A
*L
13
21
I/O 0 ~ I/O 7
4
(512 + 16)Byte x 262,144
Global Buffers
Page Register & S/A
I/O Buffers & Latches
1,024M + 32M Bit
I/O 5
A
A
A
*L
14
22
NAND Flash
5
8 bit
Y-Gating
ARRAY
1 Block = 32 Pages
(16K + 512) Byte
1 Page = 528 Bytes
1 Block = 528 B x 32 Pages
1 Device = 528B x 32Pages x 8,192 Blocks
I/O 6
A
A
A
*L
15
23
6
= (16K + 512) Bytes
= 1,056 Mbits
I/O 7
A
A
A
* L
FLASH MEMORY
16
24
7
Output
Driver
Column Address
Row Address
(Page Address)
V
V
CC
SS
I/0 0
I/0 7