LC89075W-H SANYO [Sanyo Semicon Device], LC89075W-H Datasheet - Page 29

• Manufacturer Part Number: LC89075W-H
• Description: Digital Audio Interface Receiver with Stereo ADC and Audio Selector
• Manufacturer: SANYO [Sanyo Semicon Device]

10.2 S/PDIF Input/Output
10.2.1 S/PDIF Input Reception Range
• The input data reception range is shown below.
• The PLL output clock is output to each pin according to the RXCKAT, RXCKDV[1:0] and RXMCK[1:0] register
• The fs reception range of input data can be limited to within the above PLL output clock setting range. This setting is
10.2.2 S/PDIF Input/Output Pins (RXIN1 to RXIN8, RXIN1A to RXIN3A, MPIO[4:1], RXOUT, MPOUT4)
• Up to 15 digital data input pins are provided. In addition, two S/PDIF output pins are provided.
• RXIN[8:1] pins are TTL level compatible input pins with 5V tolerance voltage.
• MPIO[4:1] are TTL level compatible input pins with 3.3V tolerance voltage.
• MPIO[4:1] must be set to input with the MPSEL[1:0] register.
• RXIN[3:1]A are TTL level with 3.3V tolerance voltage or coaxial compatible input pins.
• Each RXIN[3:1]A change the function by the RX1ASEL, RX2ASEL and RX3ASEL registers.
• In the initial status, RXIN[3:1]A are set to TTL level compatible input pins.
• When RXIN[3:1]A are used for coaxial input, RXIN[3:1]A must connect terminator and DC cutting capacity.
• All the S/PDIF input pins can receive 32kHz to 192kHz data.
• RXOUT and MPOUT4 are input selector output pins, and output the S/PDIF through data.
• The demodulated data and the through output data can be selected separately.
• The demodulated data is selected with the RXDSEL[3:0] register.
• The RXOUT pin output data is selected with the RXTHR1[3:0] register.
• The MPOUT4 pin output data is selected with the RXTHR2[3:0] register.
• The S/PDIF through data output from the MPOUT4 pin is set with the SW2SEL[2:0] register.
• The RXDSEL[3:0] register can also be set so that all input digital data is deselected. This enables input data switching
• The RXTHR1[3:0] and RXTHR2[3:0] registers are initially set so that RXOUT and MPOUT4 output “L.”
settings.
carried out with the RXLIM[1:0] register. When this function is used, input data exceeding the set range is considered
as an error, and the clock source is automatically switched to the XIN source.
via the no-signal input status.
When not using RXOUT and MPOUT4, muting these pins is recommended.
Coaxial
Optical
50Ω
PLL Output Clock Setting
Table 10.4 S/PDIF Reception Range (“RXLIM[1:0]=00”)
0.01μF to 0.1μF
512fs
Figure 10.5 S/PDIF Input Circuit Example
10 to 100Ω
LC89075W-H
RXIN[3:1]A
RXIN[8:1]
Setting examples:
LC89075W-H
“RX1ASEL=1”
“RX2ASEL=1”
“RX3ASEL=1”
Input Data Reception Range
32kHz to 192kHz
RXOUT
MPOUT4
No.A1858-29/69