T5743P3 ATMEL [ATMEL Corporation], T5743P3 Datasheet - Page 22

• Manufacturer Part Number: T5743P3
• Description: UHF ASK/FSK Receiver
• Manufacturer: ATMEL [ATMEL Corporation]

Figure 28. Output of Digital Noise at the End of the Data Stream
Figure 29. Automatic Noise Suppression
Figure 30. Occurence of a Pulse at the End of the Data Stream
Controlled Noise Suppression
by the Microcontroller (see
Figure 31)
22
T5743
Data_out (DATA)
DATA_CLK
Data_out (DATA)
Data_out (DATA)
DATA_CLK
DATA_CLK
DATA_CLK
Dem_out
Data_out (DATA)
Bit-check
Bit-check
mode
Bit-check
mode
mode
Bit check ok
Bit check ok
Bit check ok
Preburst
Preburst
Preburst
Receiving mode,
data clock control
logic active
Receiving mode,
data clock control
logic active
Receiving mode,
data clock control
logic active
If the bit Noise_Disable (see Table 10) in the OPMODE register is set to 0, digital noise
appears at the end of a valid data stream. To suppress the noise, the Pin POLL-
ING/_ON must be set to Low. The receiver remains in receiving mode. Then, the OFF-
command causes the change to the start-up mode. The programmed sleep time (see
Table 8) will not be executed because the level at Pin POLLING/_ON is low, but the bit
check is active in that case. The OFF-command activates the bit check also if the Pin
POLLING/_ON is held to Low. The receiver changes back to receiving mode if the bit
check was successful. To activate the polling mode at the end of the data transmission,
the Pin POLLING/_ON must be set to High.
This way to suppress the noise is recommended if the data stream is not Manchester or
Bi-phase coded.
'1'
Receiving mode,
data clock control
logic active
Data stream
Data
Data
Data
Timing error
'1'
'1'
Digital Noise
Digital Noise
(t
ee
< T
T
Receiving mode,
bit check aktive
ee
Receiving mode,
bit check aktive
Lim_min
Bit-check
mode
OR T
Lim_max
Digital Noise
T
Digital Noise
< t
Pulse
ee
< T
Bit check ok
Bit check ok
Lim_min_2T
Bit check ok
Digital noise
OR t
Preburst
Preburst
Bit-check mode
Preburst
ee
Receiving mode,
data clock control
logic active
Receiving mode,
data clock control
logic active
Receiving mode,
data clock control
logic active
> T
Lim_max_2T
)
Data
Data
Data
Receiving mode,
bit check aktive
Receiving mode,
bit check aktive
Digital Noise
Digital Noise
Bit-check
mode
4569A–RKE–12/02