K6R1008V1C SAMSUNG [Samsung semiconductor], K6R1008V1C Datasheet
K6R1008V1C
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K6R1008V1C Summary of contents
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... K6R1008V1C-C/C-L, K6R1008V1C-I/C-P Document Title 128Kx8 Bit High-Speed CMOS Static RAM(3.3V Operating). Operated at Commercial and Industrial Temperature Ranges. Revision History Rev. No. History Rev. 0.0 Initial release with Preliminary. Rev. 1.0 Relax DC characteristics. Item I 12ns CC 15ns 20ns Rev. 2.0 Release to Final Data Sheet. 2.1. Delete Preliminary. 2.2. Changed Standby Current. ...
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... The K6R1008V1C is a 1,048,576-bit high-speed Static Random Access Memory organized as 131,072 words by 8 bits. The K6R1008V1C uses 8 common input and output lines and has an output enable pin which operates faster than address access time at read cycle. The device is fabricated using SAM- SUNG s advanced CMOS process and designed for high- speed circuit technology ...
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... K6R1008V1C-C/C-L, K6R1008V1C-I/C-P ABSOLUTE MAXIMUM RATINGS* Parameter Voltage on Any Pin Relative Voltage on V Supply Relative Power Dissipation Storage Temperature Operating Temperature Commercial Industrial * Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied ...
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... K6R1008V1C-C/C-L, K6R1008V1C-I/C-P AC CHARACTERISTICS ( TEST CONDITIONS* Parameter Input Pulse Levels Input Rise and Fall Times Input and Output timing Reference Levels Output Loads * bove test conditions are also applied at industrial temperature range. The a Output Loads(A) D OUT Capacitive Load consists of all components of the test environment ...
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... K6R1008V1C-C/C-L, K6R1008V1C-I/C-P WRITE CYCLE* Parameter Symbol Write Cycle Time t WC Chip Select to End of Write t CW Address Set-up Time t Address Valid to End of Write t AW Write Pulse Width(OE High Write Pulse Width(OE Low) t WP1 Write Recovery Time t WR Write to Output High-Z t WHZ ...
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... K6R1008V1C-C/C-L, K6R1008V1C-I/C-P NOTES(READ CYCLE high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first transition address and t are defined as the time at which the outputs achieve the open circuit condition and are not referenced to V ...
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... K6R1008V1C-C/C-L, K6R1008V1C-I/C-P TIMING WAVEFORM OF WRITE CYCLE(3) Address CS WE High-Z Data in High-Z Data out NOTES(WRITE CYCLE) 1. All write cycle timing is referenced from the last valid address to the first transition address write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low ; ...
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... K6R1008V1C-C/C-L, K6R1008V1C-I/C-P DATA RETENTION CHARACTERISTICS* Parameter Symbol V for Data Retention CC Data Retention Current Data Retention Set-Up Time Recovery Time * The above parameters are also guaranteed at industrial temperature range. Data Retention Characteristic is for L-ver only. DATA RETENTION WAVE FORM CS controlled ...
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... K6R1008V1C-C/C-L, K6R1008V1C-I/C-P PACKAGE DIMENSIONS 32-SOJ-400 #32 11.18 0.12 0.440 0.005 #1 +0.10 0.43 -0.05 0. +0.004 0.017 0.0375 -0.002 32-TSOP2-400CF #32 #1 21.35 0.841 20.95 0.825 0.95 0. 0.10 0.037 0.016 0.004 #17 #16 21.36 MAX 0.841 20.95 0.12 0.825 0.005 1.30 ( 0.051 1.30 ( 0.051 +0.10 0.71 -0.05 1.27 +0.004 0.028 0.050 -0.002 #17 11.76 0.20 0.463 0.008 #16 MAX 0.10 0.004 1.00 0.10 0.039 0.047 0.004 1.27 0.05 MIN 0.050 0.002 - 9 - PRELIMINARY PRELIMINARY ...