LH5324C00 SHARP [Sharp Electrionic Components], LH5324C00 Datasheet

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LH5324C00

Manufacturer Part Number
LH5324C00
Description
CMOS 24M (1.5M x 16) MROM
Manufacturer
SHARP [Sharp Electrionic Components]
Datasheet
LH5324C00
FEATURES
DESCRIPTION
ROM organized as 1,572,864
using silicon-gate CMOS process technology.
The LH5324C00 is a 24M-bit mask-programmable
1,572,864
Access time: 120 ns (MAX.)
Supply current:
TTL compatible I/O
Three-state output
Single +5 V Power supply
Static operation
When the address input at both A
A
impedance irrespective of CE or OE.
Package:
Others:
20
– Operating: 80 mA (MAX.)
– Standby: 100 A (MAX.)
– Non programmable
– Not designed or rated as radiation
– CMOS process (P type silicon
42-pin, 600-mil DIP
is high level, outputs become high
hardened
substrate)
16 bit organization
16 bits. It is fabricated
19
and
PIN CONNECTIONS
42-PIN DIP
CMOS 24M (1.5M
Figure 1. Pin Connections
GND
A
D
A
OE
D
CE
D
D
D
D
D
A
A
A
A
A
A
D
A
A
17
18
10
11
7
4
0
0
8
9
2
3
6
5
3
2
1
1
1
11
12
13
14
19
2
3
4
5
6
7
8
9
10
15
16
17
18
20
21
40
37
36
34
33
32
30
28
27
26
25
24
23
42
39
38
35
29
22
31
41
D
D
D
D
D
D
D
A
A
A
GND
D
V
A
A
A
A
A
A
A
A
12
7
14
6
13
5
12
4
19
8
9
10
11
13
14
15
16
20
15
CC
16) MROM
TOP VIEW
5324C00-1
1

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LH5324C00 Summary of contents

Page 1

... DIP Others: – Non programmable – Not designed or rated as radiation hardened – CMOS process (P type silicon substrate) DESCRIPTION The LH5324C00 is a 24M-bit mask-programmable ROM organized as 1,572,864 16 bits fabricated using silicon-gate CMOS process technology. CMOS 24M (1.5M PIN CONNECTIONS 42-PIN DIP A ...

Page 2

... Address input Data output Chip enable input 2 MEMORY MATRIX (1,572,864 x 16) COLUMN SELECTOR TIMING SENSE AMPLIFIER GENERATOR GND CC Figure 2. LH5324C00 Block Diagram SIGNAL GND CMOS 24M (1.5M x 16) MROM ...

Page 3

... CONDITIONS MIN. 2.2 -0 -400 OUT 120 0 MHz LH5324C00 = MAX. UNIT NOTE 100 ...

Page 4

... LH5324C00 AC ELECTRICAL CHARACTERISTICS (V PARAMETER SYMBOL Read cycle time t RC Address access time t AA Chip enable access time t ACE Output enable delay time t OE Output hold time CHZ Output floating time t OHZ t AHZ NOTE: 1. Determined by the time for the output to be opened. (Irrespective of output voltage) ...

Page 5

... NOTE: The output data becomes valid when the last intervals have concluded. AA ACE OE HI-Z = High impedance (NOTE) t ACE (NOTE (NOTE) DATA VALID Figure 3. Byte Mode DATA VALID Figure 4. Word Mode LH5324C00 t CHZ t OHZ t OH HI-Z 5324C00-3 t CHZ t OHZ t AHZ HI-Z 5324C00-4 5 ...

Page 6

... TYP. 0.40 [0.016] MAXIMUM LIMIT DIMENSIONS IN MM [INCHES] MINIMUM LIMIT ORDERING INFORMATION LH5324C00 D Device Type Package Example: LH5324C00D (CMOS (24M 1.5M x 16) Mask-Programmable ROM, 42-pin, 600-mil DIP) 6 CMOS 24M (1.5M x 16) MROM 22 13.45 [0.530] 12.95 [0.510] 0.30 [0.012] 0.20 [0.008] 21 4.55 [0.179] 3.95 [0.156] 5.40 [0.213] 4.80 [0.189] 3.55 [0.140] 2 ...

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