MBM29F400TA12PFTN Fujitsu, MBM29F400TA12PFTN Datasheet
MBM29F400TA12PFTN
Manufacturer Part Number
MBM29F400TA12PFTN
Description
TSSOP48
Manufacturer
Fujitsu
Datasheet
1.MBM29F400TA12PFTN.pdf
(46 pages)
Specifications of MBM29F400TA12PFTN
Date_code
09+
FUJITSU SEMICONDUCTOR
FLASH MEMORY
CMOS
4M (512K
MBM29F400TA/MBM29F400BA
Embedded Erase
DISTINCTIVE CHARACTERISTICS
• Single 5.0 V read, write, and erase
• Compatible with JEDEC-standard commands
• Compatible with JEDEC-standard word-wide pinouts
• Minimum 100,000 write/erase cycles
• High performance
• Sector erase architecture
• Boot Code Sector Architecture
• Embedded Erase
• Embedded Program
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Low power consumption
• Low V
• Sector protection
• Temporary sector unprotection
• Erase Suspend/Resume
DATA SHEET
Minimizes system level power requirements
Uses same software commands as E
48-pin TSOP (Package suffix: PFTN–Normal Bend Type, PFTR–Reversed Bend Type)
44-pin SOP (Package suffix: PF)
70 ns maximum access time
One 16K byte, two 8K bytes, one 32K byte, and seven 64K bytes.
Any combination of sectors can be concurrently erased. Also supports full chip erase.
T = Top sector
B = Bottom sector
Automatically pre-programs and erases the chip or any sector
Automatically writes and verifies data at specified address
20 mA typical active read current for Byte Mode
28 mA typical active read current for Word Mode
30 mA typical write/erase current
25 A typical standby current
Hardware method disables any combination of sectors from write or erase operations
Hardware method enable temporarily any combination of sectors from write or erase operations.
Suspends the erase operation to allow a read in another sector within the same device
CC
TM
write inhibit
and Embedded Program
TM
Algorithms
TM
Algorithms
3.2 V
TM
are trademarks of Advanced Micro Devices, Inc.
2
PROMs
8/256K
16)
DS05-20812-3E
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