HCTS540DMSR INTERSIL [Intersil Corporation], HCTS540DMSR Datasheet

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HCTS540DMSR

Manufacturer Part Number
HCTS540DMSR
Description
Radiation Hardened Inverting Octal Buffer/Line Driver, Three-State
Manufacturer
INTERSIL [Intersil Corporation]
Datasheet
September 1995
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
Features
• 3 Micron Radiation Hardened CMOS SOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm
• Single Event Upset (SEU) Immunity < 2 x 10
• Dose Rate Survivability: >1 x 10
• Dose Rate Upset >10
• Latch-Up Free Under Any Conditions
• Fanout (Over Temperature Range)
• Military Temperature Range: -55
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• LSTTL Input Compatibility
• Input Current Levels Ii
Description
The Intersil HCTS540MS is a Radiation Hardened inverting
Octal Buffer/Line Driver, with two active-low output enables.
The output enable pins (OE1 and OE2) control the three-
state outputs. If either enable is high the outputs will be in
the high impedance state. For data output both enables
(OE1 and OE2) must be low.
The HCTS540MS utilizes advanced CMOS/SOS technology
to achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCTS540MS is supplied in a 20 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
Ordering Information
HCTS540DMSR
HCTS540KMSR
HCTS540D/Sample
HCTS540K/Sample
HCTS540HMSR
Bit-Day (Typ)
- Bus Driver Outputs 15 LSTTL Loads
- VIL = 0.8V Max
- VIH = VCC/2 Min
PART NUMBER
10
RAD (Si)/s 20ns Pulse
5 A at VOL, VOH
TEMPERATURE RANGE
12
o
C to +125
RAD (Si)/s
-55
-55
o
o
C to +125
C to +125
+25
+25
+25
o
o
o
o
C
C
C
C
2
Inverting Octal Buffer/Line Driver, Three-State
/mg
-9
o
o
C
C
Errors/
1
Pinouts
Intersil Class S Equivalent
Intersil Class S Equivalent
Sample
Sample
Die
HCTS540MS
GND
OE1
SCREENING LEVEL
A0
A1
A2
A3
A4
A5
A6
A7
MIL-STD-1835 CDFP4-F20, LEAD FINISH C
MIL-STD-1835 CDIP2-T20, LEAD FINISH C
FLATPACK PACKAGE (FLATPACK)
20 LEAD CERAMIC DUAL-IN-LINE
20 LEAD CERAMIC METAL SEAL
METAL SEAL PACKAGE (SBDIP)
GND
OE1
A0
A1
A2
A3
A4
A5
A6
A7
10
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
10
TOP VIEW
TOP VIEW
Radiation Hardened
20 Lead SBDIP
20 Lead Ceramic Flatpack
20 Lead SBDIP
20 Lead Ceramic Flatpack
Die
20
19
18
17
16
15
14
13
12
11
20
19
18
17
16
15
14
13
12
11
Spec Number
VCC
OE2
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
File Number
PACKAGE
518631
VCC
OE2
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
2232.2

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HCTS540DMSR Summary of contents

Page 1

... CMOS/SOS Logic Family. The HCTS540MS is supplied lead Ceramic flatpack (K suffi SBDIP Package (D suffix). Ordering Information PART NUMBER TEMPERATURE RANGE HCTS540DMSR HCTS540KMSR HCTS540D/Sample HCTS540K/Sample HCTS540HMSR CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. ...

Page 2

Functional Diagram INPUTS ( OE1 1 OE2 19 OE1 H = High Level L = Low Level X = Don’t Care Z = High Impedance HCTS540MS ONE OF 8 BUFFERS TRUTH TABLE OE2 AN L ...

Page 3

Absolute Maximum Ratings Supply Voltage (VCC -0.5V to +7.0V Input Voltage Range, All Inputs . . ...

Page 4

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL Data to Output TPHL VCC = 4.5V TPLH VCC = 4.5V Enable to Output TPZL VCC = 4.5V TPZH VCC = 4.5V Disable to Output TPLZ, VCC = 4.5V TPHZ NOTES: 1. ...

Page 5

TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) PARAMETER SYMBOL Output Voltage High VOH VCC = 4.5V or 5.5V, VIH = VCC/2, VIL = 0.8V, IOH = -50 A Input Leakage Current IIN VCC = 5.5V, VIN = VCC ...

Page 6

CONFORMANCE GROUPS METHOD Group E Subgroup 2 5005 NOTE: 1. Except FN test which will be performed 100% Go/No-Go. TABLE 8. STATIC BURN-IN AND DYNAMIC BURN-IN TEST CONNECTIONS OPEN GROUND STATIC BURN-IN I TEST CONNECTIONS (Note ...

Page 7

Intersil Space Level Product Flow - ‘MS’ Wafer Lot Acceptance (All Lots) Method 5007 (Includes SEM) GAMMA Radiation Verification (Each Wafer) Method 1019, 4 Samples/Wafer, 0 Rejects 100% Nondestructive Bond Pull, Method 2023 Sample - Wire Bond Pull Monitor, Method ...

Page 8

AC Timing Diagrams VIH INPUT VS VIL TPLH VOH VS OUTPUT VOL TTLH VOH 80% 20% OUTPUT VOL AC VOLTAGE LEVELS PARAMETER HCTS VCC 4.50 VIH 3.00 VS 1.30 VIL 0 GND 0 Three-State Low Timing Diagrams VIH INPUT VS ...

Page 9

Three-State High Timing Diagrams VIH INPUT VS VIL TPHZ VOH VW OUTPUT VOZ THREE-STATE HIGH VOLTAGE LEVELS PARAMETER HCTS VCC 4.50 VIH 3.00 VS 1.30 VT 1.30 VW 3.60 VIL 0 GND 0 All Intersil semiconductor products are manufactured, assembled ...

Page 10

Die Characteristics DIE DIMENSIONS: 101 x 85mils METALLIZATION: Type: SiAl Å Å Metal Thickness: 11k 1k GLASSIVATION: Type: SiO 2 Å Å Thickness: 13k 2.6k WORST CASE CURRENT DENSITY <2 A/cm BOND PAD SIZE: 100 m ...

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