HCTS393HMSR INTERSIL [Intersil Corporation], HCTS393HMSR Datasheet

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HCTS393HMSR

Manufacturer Part Number
HCTS393HMSR
Description
Radiation Hardened Dual 4-Stage Binary Counter
Manufacturer
INTERSIL [Intersil Corporation]
Datasheet
August 1995
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
Features
• 3 Micron Radiation Hardened CMOS SOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm
• Single Event Upset (SEU) Immunity < 2 x 10
• Dose Rate Survivability: >1 x 10
• Dose Rate Upset >10
• Latch-Up Free Under Any Conditions
• Fanout (Over Temperature Range)
• Military Temperature Range: -55
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• LSTTL Input Compatibility
• Input Current Levels Ii
Description
The Intersil HCTS393MS is a Radiation Hardened 4-stage
riple-carry binary counter. All counter stages are master-
slave flip-flop. The state of the stage advances one count on
the negative transition of each clock pulse. A high voltage
level on the MR line resets all counters to their zero state. All
inputs and outputs are buffered.
The HCTS393MS utilizes advanced CMOS/SOS technology
to achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCTS393MS is supplied in a 14 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
Ordering Information
HCTS393DMSR
HCTS393KMSR
HCTS393D/Sample
HCTS393K/Sample
HCTS393HMSR
Bit-Day (Typ)
- Standard Outputs: 10 LSTTL Loads
- VIL = 0.8V Max
- VIH = VCC/2 Min
PART NUMBER
10
RAD (Si)/s 20ns Pulse
5 A at VOL, VOH
TEMPERATURE RANGE
12
o
C to +125
-55
-55
RAD (Si)/s
o
o
C to +125
C to +125
+25
+25
+25
o
o
o
o
C
C
C
C
2
/mg
-9
o
o
C
C
Errors/
672
Pinouts
Intersil Class S Equivalent
Intersil Class S Equivalent
Sample
Sample
Die
HCTS393MS
MR 1
CP 1
Q0 1
Q1 1
Q2 1
Q3 1
GND
SCREENING LEVEL
FLATPACK PACKAGE (FLATPACK)
14 LEAD CERAMIC DUAL-IN-LINE
14 LEAD CERAMIC METAL SEAL
METAL SEAL PACKAGE (SBDIP)
Dual 4-Stage Binary Counter
MR 1
CP 1
GND
Q0 1
Q1 1
Q2 1
Q3 1
MIL-STD-1835 CDFP3-F14
MIL-STD-1835 CDIP2-T14
1
2
3
4
5
6
7
1
2
3
4
5
6
7
TOP VIEW
TOP VIEW
Radiation Hardened
14 Lead SBDIP
14 Lead Ceramic Flatpack
14 Lead SBDIP
14 Lead Ceramic Flatpack
Die
14
13
12
11
10
9
8
14
13
12
11
10
Spec Number
9
8
File Number
PACKAGE
VCC
2 CP
2 MR
2 Q0
2 Q1
2 Q2
2 Q3
VCC
2 CP
2 MR
2 Q0
2 Q1
2 Q2
2 Q3
518633
3071.1

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HCTS393HMSR Summary of contents

Page 1

... The HCTS393MS is supplied lead Ceramic flatpack (K suffi SBDIP Package (D suffix). Ordering Information PART NUMBER TEMPERATURE RANGE HCTS393DMSR HCTS393KMSR HCTS393D/Sample HCTS393K/Sample HCTS393HMSR CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 HCTS393MS Pinouts 2 /mg -9 Errors/ ...

Page 2

Functional Diagram 1(13) CP 2(12) MR TRUTH TABLE OUTPUTS CP COUNT ...

Page 3

Absolute Maximum Ratings Supply Voltage (VCC -0.5V to +7.0V Input Voltage Range, All Inputs . . ...

Page 4

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL CPn to Q0 TPHL VCC = 4.5V TPLH CPn to Q1 TPHL VCC = 4.5V TPLH CPn to Q2 TPHL VCC = 4.5V TPLH CPn to Q3 TPHL VCC = 4.5V TPLH ...

Page 5

TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL Quiescent Current ICC VCC = 5.5V, VIN = VCC or GND Output Current (Sink) IOL VCC = 4.5V, VIN = VCC or GND, VOUT = 0.4V Output Current IOH VCC ...

Page 6

CONFORMANCE GROUPS Initial Test (Preburn-In) Interim Test I (Postburn-In) Interim Test II (Postburn-In) PDA Interim Test III (Postburn-In) PDA Final Test Group A (Note 1) Group B Subgroup B-5 Subgroup B-6 Group D NOTE: 1. Alternate group A inspection in ...

Page 7

Intersil Space Level Product Flow - ‘MS’ Wafer Lot Acceptance (All Lots) Method 5007 (Includes SEM) GAMMA Radiation Verification (Each Wafer) Method 1019, 4 Samples/Wafer, 0 Rejects 100% Nondestructive Bond Pull, Method 2023 Sample - Wire Bond Pull Monitor, Method ...

Page 8

AC Timing Diagrams tr tf INPUT LEVEL TPLH Qn VS FIGURE 1. CLOCK PRE-REQUISITE AND PROPAGATION DE- LAY, AND OUTPUT-TRANSITION TIMES TTLH VOH 80% 20% OUTPUT VOL FIGURE 3. OUTPUT TRANSITION TIME AC Load Circuit HCTS393MS ...

Page 9

Die Characteristics DIE DIMENSIONS mils METALLIZATION: Type: AlSi Å Å Metal Thickness: 11k 1k GLASSIVATION: Type: SiO 2 Å Å Thickness: 13k 2.6k WORST CASE CURRENT DENSITY <2 A/cm BOND PAD SIZE: 100 ...

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