HCTS283D/SAMPLE INTERSIL [Intersil Corporation], HCTS283D/SAMPLE Datasheet

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HCTS283D/SAMPLE

Manufacturer Part Number
HCTS283D/SAMPLE
Description
Radiation Hardened 4 Bit Binary Full Adder with Fast Carry
Manufacturer
INTERSIL [Intersil Corporation]
Datasheet
September 1995
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
Features
• 3 Micron Radiation Hardened CMOS SOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm
• Single Event Upset (SEU) Immunity < 2 x 10
• Dose Rate Survivability: >1 x 10
• Dose Rate Upset >10
• Latch-Up Free Under Any Conditions
• Military Temperature Range: -55
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• LSTTL Input Compatibility
• Input Current Levels Ii
Description
The Intersil HCTS283MS is a Radiation Hardened 4 bit
binary full adder with fast carry that adds two 4 bit binary
numbers and generates a carry-out bit if the sum exceeds 15.
This device can be used in positive or negative logic. When
using positive logic the carry-in input must be tied low, if
there is no carry-in.
The HCTS283MS utilizes advanced CMOS/SOS technology
to achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family .
The HCTS283MS is supplied in a 16 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
Ordering Information
HCTS283DMSR
HCTS283KMSR
HCTS283D/Sample
HCTS283K/Sample
HCTS283HMSR
Bit-Day (Typ)
- VIL = 0.8V Max
- VIH = VCC/2V Min
PART NUMBER
|
Intersil (and design) is a trademark of Intersil Americas Inc.
TM
10
RAD (Si)/s 20ns Pulse
5 A at VOL, VOH
TEMPERATURE RANGE
12
o
C to +125
RAD (Si)/s
-55
-55
o
o
C to +125
C to +125
+25
+25
+25
o
o
o
o
C
C
C
C
2
/mg
-9
o
o
C
C
Errors/
1
4 Bit Binary Full Adder with Fast Carry
Pinouts
Intersil Class S Equivalent
Intersil Class S Equivalent
Sample
Sample
Die
HCTS283MS
GND
CIN
SCREENING LEVEL
B1
A1
A0
B0
S1
S0
MIL-STD-1835 CDIP2-T16, LEAD FINISH C
MIL-STD-1835 CDIP2-T16, LEAD FINISH C
FLATPACK PACKAGE (FLATPACK)
16 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
16 LEAD CERAMIC METAL SEAL
GND
CIN
B1
A1
A0
B0
S1
S0
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
TOP VIEW
TOP VIEW
Radiation Hardened
16 Lead SBDIP
16 Lead Ceramic Flatpack
16 Lead SBDIP
16 Lead Ceramic Flatpack
Die
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
Spec Number
VCC
B2
A2
S2
A3
B3
S3
COUT
PACKAGE
FN3381.1
VCC
B2
A2
S2
A3
B3
S3
COUT
518641

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HCTS283D/SAMPLE Summary of contents

Page 1

... The HCTS283MS is supplied lead Ceramic flatpack (K suffix SBDIP Package (D suffix). Ordering Information PART NUMBER TEMPERATURE RANGE HCTS283DMSR HCTS283KMSR HCTS283D/Sample HCTS283K/Sample HCTS283HMSR CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. | 1-888-INTERSIL or 321-724-7143 Intersil (and design trademark of Intersil Americas Inc. ...

Page 2

Functional Diagram CIN GND 16 VCC S0 4 HCTS283MS COUT 10 9 518641 Spec Number ...

Page 3

Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V Input Voltage ...

Page 4

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL Propagation Delay TPLH VCC = 4.5V, VIH = 3.0V, CIN to S0 VIL = 0V TPHL VCC = 4.5V, VIH = 3.0V, VIL = 0V Propagation Delay TPLH VCC = 4.5V, VIH ...

Page 5

TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL Quiescent Current ICC VCC = 5.5V, VIN = VCC or GND Delta ICC DICC VCC = 5.5V, VIN = VCC or GND, 1 Input at 2.4V Output Current (Sink) IOL ...

Page 6

CONFORMANCE GROUPS Initial Test (Preburn-In) Interim Test I (Postburn-In) Interim Test II (Postburn-In) PDA Interim Test III (Postburn-In) PDA Final Test Group A (Note 1) Group B Subgroup B-5 Subgroup B-6 Group D NOTES: 1. Alternate Group A, in accordance ...

Page 7

Intersil Space Level Product Flow - ‘MS’ Wafer Lot Acceptance (All Lots) Method 5007 (Includes SEM) GAMMA Radiation Verification (Each Wafer) Method 1019, 4 Samples/Wafer, 0 Rejects 100% Nondestructive Bond Pull, Method 2023 Sample - Wire Bond Pull Monitor, Method ...

Page 8

Propagation Delay Timing Diagram and Load Circuit VIH INPUT VS VSS TPLH VOH VS OUTPUT VOL Transition Timing Diagram TTLH VOH 80% 20% OUTPUT VOL HCTS283MS DUT TPHL TTHL PARAMETER 80% VCC 20% VIH VIL VS GND 8 TEST POINT ...

Page 9

Die Characteristics DIE DIMENSIONS mils 2.21mm x 2.19mm METALLIZATION: Type: SiAl Å Å Metal Thickness: 11k 1k GLASSIVATION: Type: SiO 2 Å Å Thickness: 13k 2.6k WORST CASE CURRENT DENSITY: <2 BOND PAD SIZE: 100 ...

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