HCTS273K INTERSIL [Intersil Corporation], HCTS273K Datasheet

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HCTS273K

Manufacturer Part Number
HCTS273K
Description
Radiation Hardened Octal D Flip-Flop
Manufacturer
INTERSIL [Intersil Corporation]
Datasheet
September 1995
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com
Features
• 3 Micron Radiation Hardened CMOS SOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm
• Single Event Upset (SEU) Immunity < 2 x 10
• Dose Rate Survivability: >1 x 10
• Dose Rate Upset >10
• Latch-Up Free Under Any Conditions
• Fanout (Over Temperature Range)
• Military Temperature Range: -55
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• LSTTL Input Compatibility
• Input Current Levels Ii
Description
The Intersil HCTS273MS is a Radiation Hardened octal D flip-
flop, positive edge triggered, with reset.
The HCTS273MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCTS273MS is supplied in a 20 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
Ordering Information
HCTS273DMSR
HCTS273KMSR
HCTS273D/Sample
HCTS273K/Sample
HCTS273HMSR
Day (Typ)
- Bus Driver Outputs - 15 LSTTL Loads
- VIL = 0.8V Max
- VIH = VCC/2 Min
PART NUMBER
|
Copyright
10
©
RAD (Si)/s. 20ns Pulse
Intersil Corporation 1999
5 A at VOL, VOH
TEMPERATURE RANGE
12
o
C to +125
RAD (Si)/s
-55
-55
o
o
C to +125
C to +125
+25
+25
+25
o
o
o
o
C
C
C
C
2
/mg
-9
o
o
C
C
Errors/Bit-
1
Intersil Class S Equivalent
Intersil Class S Equivalent
Sample
Sample
Die
HCTS273MS
SCREENING LEVEL
Pinouts
GND
MR
Q0
Q1
Q2
Q3
D0
D1
D2
D3
MIL-STD-1835 CDFP4-F20, LEAD FINISH C
MIL-STD-1835 CDIP2-T20, LEAD FINISH C
FLATPACK PACKAGE (FLATPACK)
20 LEAD CERAMIC DUAL-IN-LINE
20 LEAD CERAMIC METAL SEAL
METAL SEAL PACKAGE (SBDIP)
GND
MR
Q0
Q1
Q2
Q3
D0
D1
D2
D3
10
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
10
TOP VIEW
TOP VIEW
Radiation Hardened
20 Lead SBDIP
20 Lead Ceramic Flatpack
20 Lead SBDIP
20 Lead Ceramic Flatpack
Die
Octal D Flip-Flop
Spec Number
20
19
18
17
16
15
14
13
12
11
File Number
20
19
18
17
16
15
14
13
12
PACKAGE
11
VCC
Q7
D7
D6
Q6
Q5
D5
D4
Q4
CP
518642
2274.2
VCC
Q7
D7
D6
Q6
Q5
D5
D4
Q4
CP

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HCTS273K Summary of contents

Page 1

... The HCTS273MS is supplied lead Ceramic flatpack (K suffi SBDIP Package (D suffix). Ordering Information PART NUMBER TEMPERATURE RANGE HCTS273DMSR HCTS273KMSR HCTS273D/Sample HCTS273K/Sample HCTS273HMSR CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. © | http://www.intersil.com Copyright Intersil Corporation 1999 ...

Page 2

Functional Diagram RESET (MR NOTE The level of Q established by the last low to high transition of the clock ...

Page 3

Absolute Maximum Ratings Supply Voltage (VCC -0.5V to +7.0V Input Voltage Range, All Inputs . . ...

Page 4

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL TPLH VCC = 4.5V TPHL VCC = 4. TPHL VCC = 4.5V NOTES: 1. All voltages referenced to device GND measurements assume RL = ...

Page 5

TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL Quiescent Current ICC VCC = 5.5V, VIN = VCC or GND Output Current (Sink) IOL VCC = 4.5V, VIN = VCC or GND, VOUT = 0.4V Output Current (Source) IOH ...

Page 6

CONFORMANCE GROUPS METHOD Group E Subgroup 2 5005 NOTE: 1. Except FN test which will be performed 100% Go/No-Go. TABLE 8. STATIC AND DYNAMIC BURN-IN TEST CONNECTIONS OPEN GROUND STATIC BURN-IN I TEST CONNECTIONS 12, 15, ...

Page 7

Intersil Space Level Product Flow - ‘MS’ Wafer Lot Acceptance (All Lots) Method 5007 (Includes SEM) GAMMA Radiation Verification (Each Wafer) Method 1019, 4 Samples/Wafer, 0 Rejects 100% Nondestructive Bond Pull, Method 2023 Sample - Wire Bond Pull Monitor, Method ...

Page 8

AC Timing Diagrams and Load Circuit TR TF INPUT LEVEL 90 10% 10% TW TPHL Q VS FIGURE 1. CLOCK TO OUTPUT DELAYS AND CLOCK PULSE WIDTH INPUT LEVEL TH(L) TSU( FIGURE ...

Page 9

Die Characteristics DIE DIMENSIONS: 108 x 106 mils METALLIZATION: Type: AlSi Å Å Metal Thickness: 11k 1k GLASSIVATION: Type: SiO 2 Å Å Thickness: 13k 2.6k WORST CASE CURRENT DENSITY <2 A/cm BOND PAD SIZE: 100 ...

Page 10

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, ...

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