HCTS161AHMSR INTERSIL [Intersil Corporation], HCTS161AHMSR Datasheet

HCTS161AHMSR

Manufacturer Part Number

HCTS161AHMSR

Description

Radiation Hardened Synchronous Counter

Manufacturer

INTERSIL [Intersil Corporation]

Datasheet

1.HCTS161AHMSR.pdf (9 pages)

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September 1995

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

Features

• 3 Micron Radiation Hardened CMOS SOS

• Total Dose 200K RAD (Si)

• Minimum LET for SEU Upsets: >100 MEV-cm

• Single Event Upset (SEU) Immunity < 2 x 10

• Dose Rate Survivability: >1 x 10

• Dose Rate Upset >10

• Latch-Up Free Under Any Conditions

• Military Temperature Range: -55

• Signiﬁcant Power Reduction Compared to LSTTL ICs

• DC Operating Voltage Range: 4.5V to 5.5V

• Input Logic Levels

• Input Current Levels Ii

Description

The Intersil HCTS161AMS high-reliability high-speed presettable

four-bit binary synchronous counter features asynchronous reset

and look-ahead carry logic. The HCTS161AMS has an active-low

master reset to zero, MR. A low level at the synchronous parallel

enable, SPE, disables counting and allows data at the preset

inputs (P0 - P3) to load the counter. The data is latched to the

outputs on the positive edge of the clock input, CP. The

HCTS161AMS has two count enable pins, PE and TE. TE also

controls the terminal count output, TC. The terminal count output

indicates a maximum count for one clock pulse and is used to

enable the next cascaded stage to count.

The HCTS161AMS utilizes advanced CMOS/SOS technology to

achieve high-speed operation. This device is a member of

radiation hardened, high-speed, CMOS/SOS Logic Family.

The HCTS161AMS is supplied in a 16 lead Ceramic ﬂatpack

(K sufﬁx) or a SBDIP Package (D sufﬁx).

Ordering Information

HCTS161ADMSR

HCTS161AKMSR

HCTS161AD/Sample

HCTS161AK/Sample

HCTS161AHMSR

Day (Typ)

-VIL = 0.8V Max

-VIH = VCC/2V Min

PART NUMBER

RAD (Si)/s 20ns Pulse

5 A at VOL, VOH

TEMPERATURE RANGE

C to +125

RAD (Si)/s

-55

C to +125

+25

/mg

-9

Errors/Bit-

HCTS161AMS

Intersil Class S Equivalent

Sample

Die

SCREENING LEVEL

Pinouts

GND

MIL-STD-1835 CDFP4-F16, LEAD FINISH C

MIL-STD-1835 CDIP2-T16, LEAD FINISH C

FLATPACK PACKAGE (FLATPACK)

16 LEAD CERAMIC DUAL-IN-LINE

16 LEAD CERAMIC METAL SEAL

METAL SEAL PACKAGE (SBDIP)

GND

Synchronous Counter

TOP VIEW

Radiation Hardened

16 Lead SBDIP

16 Lead Ceramic Flatpack

16 Lead SBDIP

16 Lead Ceramic Flatpack

Die

Spec Number

File Number

PACKAGE

SPE

VCC

518888

2144.2

SPE

VCC

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HCTS161AHMSR Summary of contents

Page 1

... The HCTS161AMS is supplied lead Ceramic ﬂatpack (K sufﬁ SBDIP Package (D sufﬁx). Ordering Information PART NUMBER TEMPERATURE RANGE HCTS161ADMSR HCTS161AKMSR HCTS161AD/Sample HCTS161AK/Sample HCTS161AHMSR CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 HCTS161AMS Pinouts 2 /mg -9 Errors/Bit- ...

Page 2

Absolute Maximum Ratings Supply Voltage (VCC -0.5 to +7.0V Input Voltage Range, All Inputs . ...

Page 3

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL Propagation Delay TPLH1 VCC = 4.5V, VIH = 3.0V VIL = 0V TPHL1 VCC = 4.5V, VIH = 3.0V, VIL = 0V Propagation Delay TPLH2 VCC = 4.5V, VIH ...

Page 4

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) PARAMETER SYMBOL Hold Time TSU Hold Time SPE to CP TSU Recovery Time TREC Maximum Frequency FMAX NOTE: 1. The parameters listed in Table 3 are controlled via design ...

Page 5

TABLE 5. BURN-IN AND OPERATING LIFE TEST, DELTA PARAMETERS (+25 PARAMETER ICC IOL/IOH CONFORMANCE GROUPS Initial Test (Preburn-In) Interim Test I (Postburn-In) Interim Test II (Postburn-In) PDA Interim Test III (Postburn-In) PDA Final Test Group A (Note 1) Group B ...

Page 6

TABLE 8. STATIC AND DYNAMIC BURN-IN TEST CONNECTIONS OPEN GROUND 1/2 VCC = 3V STATIC BURN-IN I TEST CONNECTIONS (Note STATIC BURN-IN II TEST CONNECTIONS (Note DYNAMIC BURN-IN ...

Page 7

Intersil Space Level Product Flow - ‘MS’ Wafer Lot Acceptance (All Lots) Method 5007 (Includes SEM) GAMMA Radiation Veriﬁcation (Each Wafer) Method 1019, 4 Samples/Wafer, 0 Rejects 100% Nondestructive Bond Pull, Method 2023 Sample - Wire Bond Pull Monitor, Method ...

Page 8

Propagation Delay Timing Diagram VIH INPUT VS VSS TPLH VOH VS OUTPUT VOL AC VOLTAGE LEVELS PARAMETER HCTS VCC 4.50 VIH 3.00 VS 1.30 VIL 0 GND 0 Pulse Width, Setup, Hold Timing Diagram Positive Edge Trigger INPUT TW VIH ...

Page 9

Die Characteristics DIE DIMENSIONS 104mils 2.19 x 2.65mm METALLIZATION: Type: AlSi Å Å Metal Thickness: 11k 1k GLASSIVATION: Type: SiO 2 Å Å Thickness: 13k 2.6k WORST CASE CURRENT DENSITY <2 A/cm BOND PAD ...

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