KMM372F803BK SAMSUNG [Samsung semiconductor], KMM372F803BK Datasheet
KMM372F803BK
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KMM372F803BK Summary of contents
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... EDO mode cycle time, t Symbol OUT stg (Voltage referenced to V Symbol (Recommended operating conditions unless otherwise noted) KMM372F803BK/BS Min Max 1080 - -- 990 - 100 - 1080 - 990 - 990 - 900 - 30 - 1080 - 990 - 2 ...
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... DRAM MODULE CAPACITANCE ( 1MHz) A Item Input capacitance[A0, B0 A12] Input capacitance[W0, W2, OE0, OE2] Input capacitance[RAS0, RAS2] Input capacitance[CAS0, CAS4] Input/Output capacitance[DQ0 - 71] AC CHARACTERISTICS ( Test condition : V /V =2.2/0.7V Parameter Random read or write cycle time Read-modify-write cycle time Access time from RAS ...
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... DRAM MODULE AC CHARACTERISTICS ( Parameter Column address to W delay time CAS precharge time to W delay time CAS setup time(CAS-before-RAS refresh) CAS hold time(CAS-before-RAS refresh) RAS to CAS precharge time Access time from CAS precharge Hyper page cycle time Hyper page read-modify-write cycle time ...
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... DRAM MODULE NOTES 1. An initial pause of 200us is required after power-up followed by any 8 RAS-only or CAS-before-RAS refresh cycles before proper device operation is achieved. 2. Input voltage levels are erence levels for measuring timing of input signals. Transi- tion times are measured between V are assumed to be 5ns for all inputs. ...
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... DRAM MODULE READ CYCLE RAS CAS RAS t CSH t CRP t RCD t RAD ASR RAH ASC t CAH ROW COLUMN ADDRESS ADDRESS t RCS CLZ t RAC OPEN KMM372F80(8)3BK/BS ...
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... DRAM MODULE WRITE CYCLE ( EARLY WRITE ) NOTE : D = OPEN OUT RAS CAS RAS t CSH t CRP t RCD t RAD ASR RAH ASC t CAH ROW COLUMN ADDRESS ADDRESS t CWL t WCS ...
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... DRAM MODULE WRITE CYCLE ( OE CONTROLLED WRITE ) NOTE : D = OPEN OUT RAS CAS RAS t CSH t CRP t RCD t RAD ASR RAH ASC t CAH ROW COLUMN ADDRESS ADDRESS t t OED ...
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... DRAM MODULE READ - MODIFY - WRITE CYCLE RAS CRP CAS ASR I/ I/OL t RAS t RCD t RAD RAH ASC CAH ROW COLUMN ADDR ADDRESS t AWD t CWD t RWD t OEA t OLZ t CLZ t CAC ...
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... DRAM MODULE HYPER PAGE READ CYCLE RAS CRP CAS ASR ROW A ADDR RASP ¡ó t CSH t t HPC HPC RCD t t CAS CAS t RAD ...
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... DRAM MODULE HYPER PAGE WRITE CYCLE ( EARLY WRITE ) NOTE : D = OPEN OUT RAS CRP CAS ASR ROW A ADDR RASP t HPC t t RCD CP t CAS t RAD t CSH RAH ...
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... DRAM MODULE HYPER PAGE READ-MODIFY-WRITE CYCLE RAS CRP CAS ASR ROW A ADDR I/ I/OL t CSH t RCD t CAS t RAD t RAH t CAH t ASC COL. ADDR t RCS t CWL CWD t AWD t RWD t OEA ...
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... DRAM MODULE HYPER PAGE READ AND WRITE MIXED CYCLE RAS CAS t RAD ASR ROW A ADDR I/ I/OL t RASP t t READ( ) READ( CAC CPA t HPC CAS CAS t RAH ...
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... DRAM MODULE RAS - ONLY REFRESH CYCLE* NOTE : W, OE Don t care OPEN OUT RAS CRP CAS ASR ROW A ADDR CAS - BEFORE - RAS REFRESH CYCLE NOTE : Don t care RAS CAS ...
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... DRAM MODULE HIDDEN REFRESH CYCLE ( READ ) RAS CAS RAS t CRP t t RCD t RAD ASR RAH ASC t CAH ROW COLUMN ADDRESS ADDRESS t RCS CLZ t RAC ...
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... DRAM MODULE HIDDEN REFRESH CYCLE ( WRITE ) NOTE : D = OPEN OUT RAS CAS RAS t CRP t t RCD t RAD ASR RAH ASC t CAH ROW COLUMN ADDRESS ADDRESS t WCS ...
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... READ-MODIFY-WRITE t WRP I/ I/OL NOTE : This timing diagram is applied to all devices besides 64M DRAM based modules. t RAS t CPT t CHR t ASC COLUMN ADDRESS t t WRH RCS t CLZ t WRH t WCS WRH RCS t AA DATA-OUT KMM372F80(8)3BK/BS ...
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... DRAM MODULE CAS - BEFORE - RAS SELF REFRESH CYCLE NOTE : OE Don t care RAS CAS CEZ TEST MODE IN CYCLE NOTE : Don t care RAS CAS CEZ ...
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... Detail A Tolerances : .005(.13) unless otherwise specified The used device is 8Mx8 DRAM with EDO mode, SOJ or TSOPII. DRAM Part No. : KMM372F803BK/BS - KM48V8104BK, KM48V8104BS. KMM372F883BK/BS - KM48V8004BK, KM48V8004BS. 5.250 (133.350) 5.014 (127.350) B 0.250 0.250 (6.350) (6 ...