AT572D940HF-CJ ATMEL [ATMEL Corporation], AT572D940HF-CJ Datasheet - Page 15

• Manufacturer Part Number: AT572D940HF-CJ
• Description: DIOPSIS 940HF ARM926EJ-S PLUS ONE GFLOPS DSP
• Manufacturer: ATMEL [ATMEL Corporation]

5. Architectural Overview
5.1
5.2
7010AS–DSP–07/07
System management
AMBA Architecture
DIOPSIS 940 HF (also named D940HF) is a high performance dual-core processing platform for
audio, communication and beam-forming applications, integrating a floating-point DSP (mAgicV
VLIW DSP) and an ARM926EJ-S Reduced Instruction Set Computer (RISC). The D940HF is
optimally suited for floating point applications with a significant need for complex domain compu-
tations like FFT and frequency domain phase-shift algorithms, requiring high dynamic range and
maximum numerical precision.
The D940HF combines the flexibility of the ARM926 RISC controller with the very high perfor-
mance of the DSP oriented VLIW architecture of mAgicV.
The availability of a standard RISC on-chip lowers software development effort for non critical
and control segments of the application. ARM926 features an MMU for virtual memory and
sophisticated memory protection, making it an ideal platform for operating systems such as
WinCE or Linux. This leaves mAgicV fully available for the numerically intensive part of the appli-
cation. The synchronization between the two processors can be either based on interrupts or on
software polling on semaphores.
The ARM926 is the D940HF master processor. The bootstrap sequence of the D940HF starts
from the bootstrap of the ARM926 from its internal ROM or external non-volatile memory. The
ARM then boots mAgicV from a non-volatile memory. After bootstrap the D940HF can start its
normal operations. The DSP side of many applications can be implemented on the D940HF by
using only the internal memory. In fact, the program memory size of 8K by 128-bit coupled with
the availability of the general purpose code compression and software pipelining of systematic
loops, gives an equivalent on-chip program memory size of about 24K cycles, corresponding to
~50K DSP assembler instructions (typical).
The architecture is based on AMBA
The AHB matrix consists of seven masters:
and of five slaves:
0. ARM926 Instruction
1. ARM926-Data
2. Peripheral Data Controller (PDC)
3. mAgicV
4. USB Host
5. Ethernet MAC 10/100
6. mAgicV JTAG
1. ARM926 ROM
2. mAgicV Registers and Memories + USB Host Registers
3. The External Bus Interface
4. The AHB-APB bridge
0. ARM926 SRAM
™
bus: the multilayer AHB matrix and the APB.
AT572D940HF Preliminary
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