EDD10161BBH-5BTS-F ELPIDA [Elpida Memory], EDD10161BBH-5BTS-F Datasheet - Page 27

• Manufacturer Part Number: EDD10161BBH-5BTS-F
• Manufacturer: ELPIDA [Elpida Memory]

Read/Write Operations
Bank Active
A read or a write operation begins with the bank active command [ACT]. The bank active command determines a
bank address and a row address. For the bank and the row, a read or a write command can be issued tRCD after
the ACT is issued.
Read Operation
The burst length (BL), the /CAS latency (CL) and the burst type (BT) of the mode register are referred when a read
command is issued. The burst length (BL) determines the length of a sequential output data by the read command
that can be set to 2, 4 or 8 . The starting address of the burst read is defined by the column address, the bank select
address (See “Pin Function”) in the cycle when the read command is issued. The data output timing is characterized
by CL and tAC. The read burst start (CL-1)
latched. The DDR Mobile RAM outputs the data strobe through DQS pins simultaneously with data. tRPRE prior to
the first rising edge of the data strobe, the DQS pins are driven low from high-Z state. This low period of DQS is
referred as read preamble. The burst data are output coincidentally at both the rising and falling edge of the data
strobe. The DQ pins become high-Z in the next cycle after the burst read operation completed. tRPST from the last
falling edge of the data strobe, the DQS pins become high-Z. This low period of DQS is referred as read postamble.
Preliminary Data Sheet E1444E30 (Ver. 30)
Command
DQS
DQ
Address
/CK
CK
NOP
Row
ACT
BL = 2
BL = 4
BL = 8
tRCD
NOP
Read Operation (Burst Length)
Column
READ
tCK + tAC (ns) after the clock rising edge where the read command is
27
tRPRE
out0 out1
out0 out1 out2 out3
out0 out1 out2 out3 out4 out5 out6 out7
NOP
EDD10161BBH-TS
tRPST
CL = 3
BL: Burst length