ISL6540CRZ INTERSIL [Intersil Corporation], ISL6540CRZ Datasheet - Page 19

• Manufacturer Part Number: ISL6540CRZ
• Description: Single-Phase Buck PWM Controller with Integrated High Speed MOSFET Driver and Pre-Biased Load Capability
• Manufacturer: INTERSIL [Intersil Corporation]

I
input voltage and a voltage rating of 1.5 times is a
conservative guideline. The RMS current rating requirement
for the input capacitor of a buck regulator is approximately
below.
I
For a through hole design, several electrolytic capacitors
(Panasonic HFQ series or Nichicon PL series or Sanyo MV-
GX or equivalent) may be needed. For surface mount
designs, solid tantalum capacitors can be used, but caution
must be exercised with regard to the capacitor surge current
rating. These capacitors must be capable of handling the
surge-current at power-up. The TPS series available from
AVX, and the 593D series from Sprague are both surge
current tested.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
IN RMS
IN RMS
FIGURE 12. INPUT-CAPACITOR CURRENT MULTIPLIER FOR
,
,
0.60
0.50
0.40
0.30
0.20
0.10
0.00
OR
=
=
0
K
I
ICM
2
O
SINGLE-PHASE BUCK CONVERTER
0.1 0.2
(
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
D D
•
–
I
O
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
2
)
+
For information regarding Intersil Corporation and its products, see www.intersil.com
0.3 0.4 0.5 0.6 0.7
DUTY CYCLE (D)
I ∆
------- - D
12
2
19
D
=
----------
VIN
0.25Io
V
O
0.8 0.9
∆
I=0Io
0.5Io
1
ISL6540
MOSFET Selection/Considerations
The ISL6540 requires 2 N-Channel power MOSFETs. These
should be selected based upon r
requirements, and thermal management requirements.
In high-current applications, the MOSFET power dissipation,
package selection and heatsink are the dominant design
factors. The power dissipation includes two loss
components; conduction loss and switching loss. The
conduction losses are the largest component of power
dissipation for both the upper and the lower MOSFETs.
These losses are distributed between the two MOSFETs
according to duty factor (see the equations below). The
upper MOSFET exhibits turn-on and turn-off switching
losses as well as the reverse recover loss, while the
synchronous rectifier exhibits body-diode conduction losses
during the leading and trailing edge dead times.
where D is the duty cycle = V
recover charge; t
dead time, and t
These equations do not include the gate-charge losses that
are proportional to the total gate charge and the switching
frequency and partially dissipated by the internal gate
resistance of the MOSFETs. Ensure that both MOSFETs are
within their maximum junction temperature at high ambient
temperature by calculating the temperature rise according to
package thermal-resistance specifications. A separate
heatsink may be necessary depending upon MOSFET
power, package type, ambient temperature and air flow.
ISL6540 DC/DC Converter Application Circuit
Detailed information on the application circuit, including a
complete Bill-of-Materials and circuit board description, can
be found in application note AN1204. See Intersil’s home
page on the web: http://www.intersil.com.
P
P
P
P
P
LOWER
DEAD
UPPER
SW
Qrr
=
=
=
Q


=
=
I
rr
O




•


I
+
I
O
I
O
VIN F
O
----- -
12
I ∆
+
2
2
ON
+
----- -
12


+
I ∆
DL
•
I ∆
------- -
•
I ∆
------- -
12
12


and t
t
& t
2
OFF
2
•
S




V
•
OFF
•
DT
r
--------------------------- -
r
-------------------------- -
+
DT
DS ON
DS ON
•


I
(
N
are the switching intervals.
(
N
t
O
are leading and trailing edge
DT
U
L
O
–
),U
----- -
12
+
),L
I ∆
/ VIN; Q
DS(ON)




I
•
•
O
•
(
D
1 D
–
t
ON
+
----- -
12
–
I ∆
P
rr
, gate supply


SW
)
•
is the reverse
•
+
VIN F
V
P
+
DL
DEAD
P
•
Qrr
•
t
DL
S
March 9, 2006
•
FN9214.0
F
S