ATSHA204 ATMEL [ATMEL Corporation], ATSHA204 Datasheet - Page 21

• Manufacturer Part Number: ATSHA204
• Description: Atmel CryptoAuthentication
• Manufacturer: ATMEL [ATMEL Corporation]

6.
6.1
6.1.1
6.1.2
I
The I
compatible at the protocol level with the AT24C16B Serial EEPROM operating at 1MHz.
The SDA pin is normally pulled high with an external pull-up resistor, as the ATSHA204 includes only an open-drain driver on
its output pin. The bus master may be either open–drain or totem pole, and if the latter, then it should be tri-stated when the
ATSHA204 is driving results on the bus. The SCL pin is an input, and must be driven both high and low at all times by an
external device
I/O Conditions
The device responds to the following I/O conditions:
Device is Asleep
When the device is asleep, it ignores all but the wake condition
The wake condition requires either that the system processor manually drive the SDA pin low for t
0x00 is transmitted at a clock rate sufficiently slow that SDA is low for a minimum period of t
the normal processor I
sequence required toput the device back into low power (sleep) mode.
When there are multiple ATSHA204 devices on the bus and the I
certain data patterns (such as 0x00) will cause all the ATSHA204 devices on the bus to wake up. Because subsequent device
addresses transmitted along the bus will only match the desired devices, the unused devices will remain idle and not cause
any bus conflicts.
In I
Device is Awake
When the device is awake, it honors the conditions listed below.
Figure 6-1. Data Bit Transfer on I
2
C Interface
2
C mode, the device will ignore a wake sequence sent when the device is already awake.
Wake:
Data Zero:
Data One:
2
C interface uses the SDA and SCL pins to indicate various I/O states to the ATSHA204. This interface is designed to be
SDA
SCL
If SDA is held low for a period greater than t
is ready to receive I
device is idle or asleep and during t
listed in Section 6.1.2, “Device is Awake,” are honored.
If SDA is low and stable while SCL goes from low to high to low, then a zero bit is being transferred on the
bus. SDA can change while SCL is low.
If SDA is high and stable while SCL goes from low to high to low, then a one bit is being transferred on the
bus. SDA can change while SCL is low.
2
C hardware and/or software can be used for device communications up to and including the I/O
Data line stable;
Data valid
2
C Interface
2
C commands. The device ignores any levels or transitions on the SCL pin when the
data allowed
Change of
WLO
. At some point during t
WLO
2
, the device exits low-power mode and, after a delay of t
C interface is run at 133KHz or slower, the transmission of
WHI
Atmel ATSHA204 [DATASHEET]
, the SCL pin is enabled and the conditions
WLO
. When the device is awake,
WLO
, or that a data byte of
8740D−CRYPTO−3/12
WHI
21
,