TSC695F ATMEL [ATMEL Corporation], TSC695F Datasheet - Page 3

• Manufacturer Part Number: TSC695F
• Description: Rad-Hard 32-bit SPARC Embedded Processor
• Manufacturer: ATMEL [ATMEL Corporation]

Table 1. Pin Descriptions (Continued)
Note:
4118H–AERO–06/03
Signal
OE
BUFFEN
DDIR
DDIR
IOSEL[3:0]
IOWR
EXMCS
BUSRDY
BUSERR
DMAREQ
DMAGNT
DMAAS
DRDY
IUERR
CPUHALT
SYSERR
SYSHALT
SYSAV
NOPAR
INULL
INST
FLUSH
DIA
RTC
RxA/RxB
TxA/TxB
GPI[7:0]
GPIINT
EXTINT[4:0]
EXTINTACK
IWDE
EWDINT
WDCLK
CLK2
SYSCLK
RESET
SYSRESET
TMODE[1:0]
DEBUG
TCK
TRST
TMS
TDI
TDO
VCCI/VSSI
VCCO/VSSO
If not specified, the output buffer type is 150 pF, the input buffer type is TTL.
Type
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Active
High
High
High
High
High
High
High
High
High
High
High
High
High
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Data buffer direction
Exchange memory chip select
Bus error
DMA address strobe
Data ready during DMA access
Processor (IU & FPU) halt and freeze
System error
System halt
Integer unit nullify cycle
Delay instruction annulled
System clock
Description
Memory output enable
Data buffer enable
Data buffer direction
I/O chip select
I/O and exchange memory write strobe
Bus ready
DMA request
DMA grant
IU error
System availability
No parity
Instruction fetch
FPU instruction flush
Real Time Clock Counter output
Receive data UART ’A’ and ’B’
Transmit data UART ’A’ and ’B’
GPI input/output
GPI interrupt
External interrupt
External interrupt acknowledge
Internal watch dog enable
External watch dog input interrupt
Watch dog clock
Double frequency clock
Output reset
System input reset
Factory test mode
Software debug mode
Test (JTAG) clock
Test (JTAG) reset
Test (JTAG) mode select
Test (JTAG) data input
Test (JTAG) data output
Main internal power
Output driver power
Used to check the execute
Output buffer: 400 pF
Functional mode=00
instruction pipeline
pull-up ≈ 37 kΩ
pull-up ≈ 37 kΩ
pull-up ≈ 37 kΩ
TSC695F
Input trigger
Input trigger
Input trigger
Input trigger
Input trigger
stage of IU
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
3