54F299 NSC [National Semiconductor], 54F299 Datasheet - Page 2

• Manufacturer Part Number: 54F299
• Description: Octal Universal Shift/Storage Register with Common Parallel I/O Pins
• Manufacturer: NSC [National Semiconductor]

Unit Loading Fan Out
Functional Description
The ’F299 contains eight edge-triggered D-type flip-flops
and the interstage logic necessary to perform synchronous
shift left shift right parallel load and hold operations The
type of operation is determined by S
the Mode Select Table All flip-flop outputs are brought out
through TRI-STATE buffers to separate I O pins that also
serve as data inputs in the parallel load mode Q
are also brought out on other pins for expansion in serial
shifting of longer words
A LOW signal on MR overrides the Select and CP inputs
and resets the flip-flops All other state changes are initiated
by the rising edge of the clock Inputs can change when the
clock is in either state provided only that the recommended
setup and hold times relative to the rising edge of CP are
observed
Pin Names
CP
DS
DS
S
MR
OE
I O
Q
0
0
0
7
1
0
S
Q
–I O
1
OE
7
2
7
Clock Pulse Input (Active Rising Edge)
Serial Data Input for Right Shift
Serial Data Input for Left Shift
Mode Select Inputs
Asynchronous Master Reset Input (Active LOW)
TRI-STATE Output Enable Inputs (Active LOW)
Parallel Data Inputs or
TRI-STATE Parallel Outputs
Serial Outputs
for DIP SOIC and Flatpak
Pin Assignment
Description
0
and S
1
Connection Diagrams
as shown in
TL F 9515–2
0
and Q
7
2
150 40(33 3)
HIGH LOW
3 5 1 083
A HIGH signal on either OE
STATE buffers and puts the I O pins in the high impedance
state In this condition the shift hold load and reset opera-
tions can still occur The TRI-STATE outputs are also dis-
abled by HIGH signals on both S
a parallel load operation
H
L
X
MR S
50 33 3
1 0 1 0
1 0 1 0
1 0 1 0
1 0 2 0
1 0 1 0
1 0 1 0
H
H
H
H
L
e
e
e
U L
e
LOW Voltage Level
HIGH Voltage Level
Immaterial
Inputs
X
H H
H
L
L
LOW-to-HIGH Clock Transition
1
S
X
H
L
L
0
54F 74F
CP
b
X
X
3 mA 24 mA (20 mA)
70 A
20 A
20 A
20 A
20 A
20 A
20 A
Output I
b
Asynchronous Reset Q
Parallel Load I O
Shift Right DS
Shift Left DS
Hold
Input I
Mode Select Table
1 mA 20 mA
Pin Assignment
b
b
b
b
b
b
b
for LCC
IH
0 65 mA
OH
0 6 mA
0 6 mA
0 6 mA
1 2 mA
0 6 mA
0 6 mA
I
IL
I
1
OL
7
0
or OE
0
Response
and S
n
Q
2
Q
7
1
0
disables the TRI-
0
Q
in preparation for
Q
– Q
Q
7
n
0
7
e
TL F 9515– 3
Q
LOW
Q
6
1
etc
etc